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High Performance New drivers Requirements Solutions - - PowerPoint PPT Presentation
High Performance New drivers Requirements Solutions - - PowerPoint PPT Presentation
High Performance New drivers Requirements Solutions Computing New workloads More computing performance (Ops Heterogeneity: per second), also for simple Generic processing Compute operations (FP16, FP8,
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High Performance Computing
Data in Data out Compute
- Starting from high
performance compute only, HPC evolves towards:
- New workloads
- Massive volume of data
Analyze New drivers Requirements Solutions
New workloads More computing performance (Ops per second), also for simple
- perations (FP16, FP8, INT…).
Energy efficiency (Ops per Watt). Heterogeneity: Generic processing + accelerators Low power design Massive volume
- f data
Increased Bytes per Flops. High bandwidth/low latency access to all data. High Bandwidth Memories and 2.5D integration
TERA1000 - CEA
<
10x energy efficiency improvement every 4 years
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CPU Cache Memory
Bus
NIC
(Network InterConnect)
NoC + LLC Cache Cache
Memory NIC
Cache Cache
Close Mem.
High Speed Link
Close Mem Close Mem Close Mem
Far Mem.
NIC
Generic processing HW accelerator
Performance = ~frequency Performance = ~nb cores Performance = ~architecture
X86 cores, RISC cores, Co-pro extension, Accelerator, GPU, FPGA, Real Time processing, Homogeneous, Heterogeneous, Data centric…
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homogeneous heterogeneous, accelerated
China US Japan
Sierra / LLNL, 2019 IBM P9 + NVidia GPU 125 petaflops (peak) (2021) Aurora / ANL Intel Xeon + Xe >1.0 exaflops (peak) (2021) Frontier / ORNL AMD CPU + GPU ~1.5 exaflops (peak) Summit / ORNL, 2019 IBM P9 + NVidia GPU 200 petaflops (peak) 148.6 petaflops (2020-2021) Tianhe-3 / NUDT Matrix-3000 >1.0 exaflops (peak) (2020-2021) Fugaku / RIKEN A64FX (Armv8.2+SVE) >0.5 exaflops Tianhe-2a /NUDT, 2018 Intel Xeon + Matrix-2000 94.97 petaflops (peak) Tianhe-2 /NUDT, 2013 Intel Xeon + KNC 33.86 petaflops (peak) K / RIKEN, 2011 SPARC64 VIIIfx 11.28 petaflops (peak) 10.51 petaflops Sugon Exa-prototype Hygon CPU + DCU NRCPC Exa-prototype SW26010 based Sunway TaihuLight /NRCPC SW26010 125.43 petaflops (peak) (?) Hygon CPU + DCU ? (?) ? ?
Europe approach ?
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* FPA : Framework Partnership Agreement * FP8 : Framework Programmes 8 for 2014-2020, succeeding FP7 (2007-2013)
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1018
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Security infrastructure
GPP processor chip
Power Management infrastructure Generic processing Accelerator Real-time processing eFPGA
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ARM ARM MPPA eFPGA EPAC HBM HBM memorie ies DDR DDR memorie ies PCIe Ie gen5 links HSL links D2D links to adja jacen ent chipl plet ets
Application Experts Architects + Model and simulation Co-design
METHODOLOGY COMPUTING UNITS SOFTWARE
Linux Operating System Programming tools & Libraries Low-level Software, Security, Power Management Automotive eHPC software support EPI Processor and Reference Hardware
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ARM ARM MPPA eFPGA EPAC HBM HBM memories DDR DDR memorie ies PCIe Ie gen5 links CCIX IX links D2D links to adja jacen ent chipl plet ets
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ARM ARM MPPA eFPGA EPAC HBM HBM memorie ies DDR DDR memorie ies PCIe Ie gen5 links HSL links D2D links to adja jacen ent chipl plet ets
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STX Bridg dge e to GPP Bridg dge e to GPP VPU VRP EPAC
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Autom
- motive
- tive
Safet fety/ y/secu security ity MCU MCU
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