FPL 2019 High-performance Decoding of Variable-length Memory Data - - PowerPoint PPT Presentation

FPL 2019

High-performance Decoding

• f Variable-length Memory Data Packets

for FPGA Stream Processing

Roberto Sierra (Integrated Systems Laboratory – UPM) Filippo Mangani (Integrated Systems Laboratory - UPM) Carlos Carreras (Integrated Systems Laboratory - UPM) Gabriel Cafgarena (University CEU San Pablo)

Motivation

• Variable-length data is used to efgiciently compress mesh-

based datasets in scientific applications (e.g., CFD)

• Streaming variable-length data from memory to FPGA

devices with a fixed-length encoding leads to wasting storage and bandwidth

• Each algorithm (e.g., 2D/3D, custom arithmetic formats)

needs a difgerent set of data packet lengths

– Known at synthesis time

Our proposal: Architecture

• Parameterizable
• Fully pipelined
• Elastic interfaces (valid/ready)
• 1 packet/line per clock cycle

Header Processor FPGA Memory Packet Decoder Packet Builder On-board Memory Packet Shifter Control Logic

Overall architecture

Example input and output

Architecture (II)

• Packet Shifuer:

– Unfortunately, no barrel shifuer

in FPGAs

– 4-1 (or 2-1) shifuer stages

• Packet Builder:

– Concatenate memory lines

• Header Decoder:

– Computes shifu and number of

lines needed by each packet

S S2i+1 2i

0..................0

i+1 2

0..................0

i 2

0..................0

i+1 + 2 i 2

Stage i

Valid Ready

Packet Shifuer stage

Payload line

Fourth Step Register Third Step Register Second Step Register First Step Register Cache Register

Control signals Extended line 6

Packet Builder

Results

• Synthesis results of example decoders

Stratix V 5SGXMABN3F45C2

• Speedup over fixed-length encoding

Thank you!