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Attacker Models for hardware or embedded security Erik Poll
Digital Security Radboud University Nijmegen
for hardware or embedded security Erik Poll Digital Security - - PowerPoint PPT Presentation
Attacker Models for hardware or embedded security Erik Poll Digital Security Radboud University Nijmegen 1 Security-sensitive hardware: examples 2 Naive attacker model Attacks on communication channels exploiting lousy crypto or insecure
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Digital Security Radboud University Nijmegen
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Attacks on communication channels exploiting lousy crypto or insecure protocols
1) mathematically strong algorithms and protocols
The mathematician’s view
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Attacks on communication channels or the end-points
1) mathematically strong algorithms and protocols, 2) secure software implementations Software engineer’s view
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Attacks on communication channel or end-points, also exploiting hardware weaknesses of end-points
1) mathematically strong algorithms and protocols 2) secure software implementations 3) secure hardware
Hardware engineer’s view
Attacker can get physical access
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As we’ll see later in this course, an implementation of a ‘secure’ cryptographic primitive (eg AES, RSA, etc) can be completely insecure on given hardware Therefore 1. Never design your own cryptographic primitives 2. Never make your own implementations of these crypto primitives Maybe the same goes for security protocols using these primitives as well...
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at are the security requirements they ensure?
w do they ensure these requirements?
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– data storage: read and/or write? – processing for and maybe also
– confidentiality – integrity/authenticity – access control
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1. key generation & distribution
2. key storage
– This is an access control problem
3. en/decryption
Smartcards provide a possible solution...
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non-repudiation with MACs
confidentiality with encryption
are not under our control,
control, namely for the keys
security problem elsewhere
functionality
integrity, non-repudiation & confidentiality by preventing read and/or write access
regulate for access to resources under our control
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computing power,...) + Pro smartcard: the hardware is more secure; on PC we can remove hard disk, access memory chips,...
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– storing data – processing data
can store but not process
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– ISO 7816
– cut-down in size
– aka proximity card or RFID transponder/tag – also possible: dual interface
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– eg OV chipkaart in NL
– eg UZI pas in NL
– new generation passports with biometric information stored
– to control access to buildings, computer networks, laptops,...
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– animal or human identification – product identification (like bar codes)
– eg eNIK (elektronische Nederlandse Identiteits Kaart)
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Functional capabilities of smartcards & RFID tags can vary a lot: 1. device just reports data – read-only file-system 2. device reports data after some access control – protected (eg password-protected) file-system
3. device can take part in crypto protocol – eg for authentication Some of these cards are programmable, some have built- in functionality which you can configure but not change Which attacks can 3 withstand, that 1 & 2 can't? Replay attacks!
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then the private key K never has to leave the card
terminal, or the card holder
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private key K CPU
challenge c response encK(c)
Capabilities of smartcards & RFID tags vary a lot:
– essentially just provide a file system – possibly with some access control or, simpler still, destructive (irreversible) writes as in old payphone-cards – configurable functionality hardwired in ROM
– contain CPU
– programmable
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– of data or functionality (incl. all software)
– resistance to copying/cloning
– non-repudiation
– being able to prove (not being able to deny) that an action has been carried out by some party
– of data, or of card/card holder, ie. anonymity
NB hardly anything is tamper-proof
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– volatile (RAM) and non-volatile (ROM+EEPROM)
possibly:
No clock, no power!
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Test & Security
Clock/ Charge Pump
Crypto coproc. RNG I/O CPU RAM EEPROM ROM memory management unit (MMU)
– for virtual machines & cryptography
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– DES in hardware takes same size as DES program code in ROM
exponentation and modulo arithmetic with large numbers
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ROM
EEPROM
RAM
Typical modern card may have 512 bytes RAM, 16K ROM, 64K EEPROM, 13.5 MHz
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lower power consumption
– stack – I/O buffer
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– "the smartcard's hard disk“
– slow: 1000x slower than RAM – has limited lifetime in # writes (> 106) – writing is two stage operation: erase & write – data retention 10-100 years – writing takes high power consumption
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Choice between program code in ROM or EEPROM has big impact on development – Program code in ROM must be suitable for mass-use
– It cannot be patched or updated
ROM towards
functionality provided by libraries or OS), and all custom functionality (the “application”) in EEPROM
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Modern alternatives for EEPROM (and ROM)
– writing 10 μs instead of 3 -10 ms for EEPROM – programming voltage 12V, against 17V for EEPROM – >100,000 writes, >10 years data retention
– Flash replacing ROM eliminates need for ROM mask & reduces development time
– writing 100 ns – programming voltage 5V
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and speed, but also in amount of chip surface required per byte: – RAM requires more space than EEPROM, – EEPROM requires more space than ROM
Size = Money
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# of write/ erase cycles writing time typical size RAM unlimited 70 ns 1700 μm2 EEPROM >104-106 3-10 ms 400 μm2 Flash >105 10 μs 200 μm2 FRAM >1010 100 ns 200 μm2 ROM
source: W. Rankl & W. Effling, Smartcard Handbook, 2nd edition, 2000
NB these numbers give a rough impression, but are outdated !!!
data, and code)
applications to be installed
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– to generate EEPROM programming voltage
– eg. division of the external clock signal to get a lower clock frequency for I/O
mode, where clock pulse is stopped, to reduce power consumption
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– checking if all RAM & EEPROM cells work – checksums for ROM and static EEPROM
attacks
be disabled before personalisation! – by writing EEPROM, blowing fuses, or even physically removing hardware
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– True RNG that is immune to external influence is hard to realise in hardware
produce different sequences of random numbers
– PRNG using seed (stored in EEPROM) supplied as part of OS initialisation
EEPROM? What if this EEPROM wears out after generating lots of random numbers? Card may have to check for this !!
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Many security protocols require the use of nonces (numbers
– to prevent replay attacks (aka ensure freshness)
1. Random numbers are only one of the ways to generate nonces 1. Another way is to simply have an increasing counter
– Eg, your bank cards all use have a counter that is included in integrity & non-repudiation checks – Wrapping around after an integer overflow is a security risk for such counters
Tested eg according to FIPS 140-1 which states single stream of 20,000 consecutive bits must pass – monobit test: 9,546 < # ones < 10,346 – poker test: frequency of 4 bits patterns:
– run test: requirements of runs (sequence of all 0's or all 1's) of lengths 1-6 – long run test: no runs 34
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Test & Security
Clock/ Charge Pump
Crypto coproc. RNG I/O CPU RAM EEPROM ROM memory management unit (MMU)