First measurements on the new V. Patel FPGA-based DIRICH MAPMT - - PowerPoint PPT Presentation

▶
first measurements on the new
SMART_READER_LITE
LIVE PREVIEW

First measurements on the new V. Patel FPGA-based DIRICH MAPMT - - PowerPoint PPT Presentation

Dec 13, 2022 9 likes •185 views

First measurements on the new FPGA-based DIRICH MAPMT readout First measurements on the new V. Patel FPGA-based DIRICH MAPMT readout Overview First test results in HADES test Vivek Patel box BergischeUniversitatWuppertal DPG Spring

slide-1
SLIDE 1

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

First measurements on the new FPGA-based DIRICH MAPMT readout

Vivek Patel

BergischeUniversitatWuppertal

DPG Spring Meeting M¨ unster,March 2017

slide-2
SLIDE 2

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Overview

HADES RICH in operation since 2000. Original design was using CsI reflective photocathode + MWPC readout for photon detection,C4F10 gas radiator, hadron blind HADES RICH is under upgrade with newly acquired H12700 MAPMTs from Hamamatsu. First beam for HADES with new photodetector is forseen to be in second half of 2018(fingers crossed..!!) Test of MAPMTs and readout electronics are currently done at Wuppertal and GSI(HADES cave).

slide-3
SLIDE 3

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

HADES-RICH upgrade

slide-4
SLIDE 4

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Readout Electronics for RICH MAPMTs

Prototype of all readout modules are in test now ..!!

slide-5
SLIDE 5

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Experimental setup in HADES cave with HADES test box

Analog part of DiRICH has been tested in HADES testbox. Single module with two active probes connected to two channels at output of preamp. The signals from preamp thus can be visualized using an oscilloscope(4GHz-R&S

  • scilloscope).

Storage of many individual traces for offline analysis. Simulate FPGA TDC offline with scope data.

slide-6
SLIDE 6

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

A typical MAPMT signal on scope

Persistancy plot of typical PMT signal After preamplification Directly before discrimination+TDC inside FPGA Picosecond pulse laser inside test setup to generate single photons

slide-7
SLIDE 7

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Time over threshold studies

ToT is an effective tool to filter our data. Operating at reasonable threshold(> noise but low enough so that we conserve maximum pulse information) this can easily differentiate between signal and crosstalk. ToT of wiggle(1-2ns) is less than that of main signal(4-5ns).

slide-8
SLIDE 8

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Time over threshold studies

ToT(Pulse width)(blue:no ToT cut red:ToT>2ns)

Pulse width(s) 1 2 3 4 5 6 7 8 9 10

9 −

10 × 500 1000 1500 2000 2500

Threshold 30mV

Pulse width(s) 1 2 3 4 5 6 7 8 9 10

9 −

10 × 100 200 300 400 500 600

Threshold 60mV

Pulse width(s) 1 2 3 4 5 6 7 8 9 10

9 −

10 × 100 200 300 400 500

Threshold 90mV

Pulse width(s) 1 2 3 4 5 6 7 8 9 10

9 −

10 × 100 200 300 400 500 600

Threshold 150mV

slide-9
SLIDE 9

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Time diff: Laser trigger↔Channel

Trig-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 50 100 150 200 250 300 350 400 450

Threshold 30mV

At low threshold we get two distinct peaks in leading edge timing one is main signal and

  • ther is wiggle.

Leading edge delayed by 3-4ns for wiggle due to inverse polarity

  • f the signal.

Wiggle signals can be supressed completely just by applying ToT cut > 2ns.

slide-10
SLIDE 10

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Time diff: Channel1↔Channel2

Channel-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 100 200 300 400 500 Threshold 30mV

On analysing data with trigger on

  • ne of the channel we found that it

showed three peak structure. The central peak here corresponds to signal(or wiggle) events in both the channels under observation. The side peaks(+/-4ns ) correspond to signal in one and wiggle in other channel. By applying ToT >2ns in both the channels(red curve) we can suppress the side peaks.

slide-11
SLIDE 11

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Expected Timing precision based on scope data

Time-diff: Laser↔ Channel(blue:no Tot cut red:ToT>2ns)

Entries 14544 Mean 09 − 2.204e Std Dev 09 − 2.051e

Trig-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 100 200 300 400 500

Entries 14544 Mean 09 − 2.204e Std Dev 09 − 2.051e

Threshold 35mV

Entries 14544 Mean 10 − 4.174e Std Dev 10 − 4.59e

Trig-Channel timing(s)

1.5 − 1 − 0.5 − 0.5 1 1.5 2 2.5

9 −

10 × 100 200 300 400 500

Entries 14544 Mean 10 − 4.174e Std Dev 10 − 4.59e

Threshold 35mV

RMS : 450ps Gauss fit : 350ps PMT-TTS: 300 Time-diff: Ch1↔Ch2(blue:no ToT cut red:ToT>2ns)

Entries 5805 Mean 10 − 7.733e RMS 09 − 3.399e

Channel-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 50 100 150 200 250 300 350

Entries 5805 Mean 10 − 7.733e RMS 09 − 3.399e

Threshold 35mV

Entries 5805 Mean 11 − 7.234e − RMS 10 − 5.662e

Channel-Channel timing(s)

1.5 − 1 − 0.5 − 0.5 1 1.5

9 −

10 × 20 40 60 80 100 120 140

Entries 5805 Mean 11 − 7.234e − RMS 10 − 5.662e

Threshold 35mV

RMS : 560ps Gauss fit : 450ps PMT-TTS: 430

slide-12
SLIDE 12

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

A step forward to real FPGA-TDC

So far all the analysis shown above were simlated TDC based

  • n Scope Data.From last few weeks full TDC using FPGA was
  • available. In following slide are the results of the same.
slide-13
SLIDE 13

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Timing Measurement using FPGA-TDC

RMS : 750ps Gauss fit : 350ps

slide-14
SLIDE 14

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Summary

First tests of readout electronics are showing promising results. Time resolution obatained using scope and that with FPGA based TDC are well in agreement with each other and also with expectations proving that the DiRICH concept will work. At this point 4 channels of FPGA has been programmed for

  • TDC. In coming days full 32 channel TDC is expected to be
  • batained for complete system tests.

The main goal now is to check the performance of the MAPMT+DiRICH readout at COSY in real beam conditions. A small protoype box has been made for beam test at COSY with 6 MAPMT and complete set of readout electornics installed in it. Currently it is under tests at Wuppertal.

slide-15
SLIDE 15

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Thank you

slide-16
SLIDE 16

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Laser trigger - channels

Leading edge timing(blue:no Tot cut red:ToT>2ns)

Trig-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 50 100 150 200 250 300 350 400 450

Threshold 30mV

Trig-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 50 100 150 200 250 300 350

Threshold 60mV

Trig-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 50 100 150 200 250 300

Threshold 90mV

Trig-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 20 40 60 80 100 120 140 160 180 200 Threshold 150mV

slide-17
SLIDE 17

First measurements

  • n the new

FPGA-based DIRICH MAPMT readout

  • V. Patel

Overview First test results in HADES test box

Channel-Channel(self trigger)

Leading edge timing(blue:no Tot cut red:ToT>2ns)

Channel-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 100 200 300 400 500 Threshold 30mV

Channel-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 20 40 60 80 100 120 Threshold 60mV

Channel-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 20 40 60 80 100 Threshold 90mV

Channel-Channel timing(s)

10 − 8 − 6 − 4 − 2 − 2 4 6 8 10

9 −

10 × 10 20 30 40 50 60 70 Threshold 150mV