Feedback System Hardware/Software Progress and Future Plans Kristin - - PowerPoint PPT Presentation

Feedback System Hardware/Software Progress and Future Plans

Kristin Pollock, John Fox, John Dusatko, Scott Johnston, John Cesaratto, Claudio Rivetta

SLAC kmpollock@stanford.edu

April 9, 2013

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 1 / 17

Outline for Talk

Updates on current work and next steps

Current hardware for SPS Feedback Demonstrator System

Features of the current system Verification of system and noise measurements

Future hardware upgrades

Wider bandwidth kickers Additional synchronization flexibility including feedback during energy ramp Additional functionality to Feedback Demonstrator System Upgrades to software (operation, user interface, analysis and feedback design)

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 2 / 17

System Diagram

4 GS/sec Feedback Control System with picosecond alignment

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 3 / 17

SPS Feedback Demonstrator System Pictures

Front Panel of System chassis. DAC daughterboard card. Inside SPS Feedback System chassis without cables. FPGA and two ADCs are shown here.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 4 / 17

SPS Feedback Demonstrator System Characterization

System tested with SPS beam in Nov 2012 and Jan/Feb 2013 Features:

Flexibility in configuration Synchronized A/D and D/A sample bunch and output to kicker 4 GS/sec. sampling rate (3.2 in current tests) Able to control 1 bunch, with FPGA reconfigurable to expand to control of additional bunches Snapshot memory captures bunch motion for up to 32k turns

• J. Dusatko testing at SLAC.
• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 5 / 17

SPS Feedback Demonstrator System Characterization

Features continued:

‘Slices’ controlled by 16 FIR filters, each with up to 16 taps Can switch between 2 sets of filters in real-time Initial control and measurement software written and tested Can be synchronized with excitation system Note: these studies use 200MHz stripline pickup as a kicker. Designing wideband kicker for further studies.

Inside SPS Feedback System chassis.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 6 / 17

Current Hardware Updates Outline

Current hardware for SPS Feedback Demonstrator System

Tested and verified feedback system Tested various filter configurations and ran feedback experimentation successfully Nonlinear (two-tone) intermodulations tests run Noise floor and dynamic range characterization Developed methods of synchronizing system with the beam Verification of equalizers Frontend hardware equalizer Backend equalizers for cabling and kicker

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 7 / 17

Hardware Verification Results: Noise Floor

ADC dynamic range is as expected > 58 dB S/N. Noise without beam is low and flat across all frequencies. DC offset of beam means we currently use half the dynamic range for ADC input. Plans to remove DC offset in future.

0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 −5 5 10 15 20 25 30 35 40 45

Beam with Pos Feedback, ADC Snapshot Memory

• Frac. Tune

Magnitude (dB)

Averaged over 4k-12k turns, an example of large signal with many modes.

0.1 0.2 0.3 0.4 0.5 −5 5 10 15 20 25 30 35 40 45

No Beam, ADC Snapshot Memory

• Frac. Tune

Magnitude (dB)

Averaged over same turns, signal without beam shows low noise.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 8 / 17

Timing Block Diagram

Feedback ADC DAC DAC

Snapshot Memory Output Memory

D3 D2 D1 Amps

Oscillo- scope

DX = Colby Delay lines Feedback Demonstration System Excitation System Pickups Kicker SPS 200MHz RF

• Inj. Fiducial
• Rev. Fiducial

Simplified block diagram of the system for demonstrating timing procedure.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 9 / 17

System Synchronization with Beam

Backend timing alignment methods developed and refined

4400 4600 4800 5000 5200 5400 5600 5800 6000 0.5 1 1.5 2 2.5 3 x 10

−3

Excitation Time Delay (ps) RMS ∆ y (a.u)

Method 1, pickup: excite with mode 1 and find minimum RMS motion at betatron tune. This method is very time consuming.

3 3.5 4 4.5 5 x 10

−8

−0.06 −0.04 −0.02 0.02 0.04 0.06

Time (s) Amplitude (arb.)

121130__035947_Ch3 Delay = 5100 ps Bunch Bunch + Excitation Excitation

Method 2, kicker load: excite with mode 1 without amplitude modulation and adjust delay until inflection point coincides. A faster more practical method.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 10 / 17

Hardware Equalizers

The cabling and pick-up (and kicker) exhibit non-linear phase response. Hardware equalizers needed for fast response. Design method developed that includes parasitic components in

• ptimization

Front-end and back-end equalizers constructed and tested.

0.5 1 1.5 2 x 10

−8

−0.15 −0.1 −0.05 0.05 0.1 0.15 0.2 0.25

Beam signal vs. Gaussian

Seconds Amplitude [Volts] Modeled Gaussian beam signal Modeled pick−up signal Measured pick−up signal

Signal with and without equalization. Equalizers shown here at CERN.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 11 / 17

Hardware Equalizer Verified

ADC snapshot with hardware front-end equalizer shows expected shape for bunch Cable equalizer for backend verified Kicker equalizer needs higher gain amplifiers, an we will re-evaluate need for backend equalizer with new kicker and amplifiers.

2 4 6 8 10 12 14 16 −100 −80 −60 −40 −20 20 Sample ADC−counts

The bunch shape as measured by the ADC shows approx. Gaussian shape.

10

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10

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−30 −20 −10 Freq (Hz) Magnitude (dB)

Backend Equalizer TF

10

8

10

9

−100 100 Freq (Hz) Phase (deg) Total Backend EQ model Total Backend EQ constructed

Transfer function for modeled and constructed backend equalizer.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 12 / 17

Next Steps for Hardware Improvements

Higher bandwidth kickers being designed by J. Cesaratto, the team at Frascati and the team at LBL

This is essential to demonstrate control of higher order instabilities as current stripline kickers only have 200MHz bandwidth. Higher power amplifier testing in preparation for new kickers

Greater flexibility of timing with energy ramping capability Additional improvements to demonstrator feedback control system

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 13 / 17

Testing New Amplifiers

Testing various amplifiers in preparation for new kickers (S. Johnston) Specifications:

100-200 Watts 40MHz-1GHz bandwidth Testing performance for higher order mode control.

• S. Johnston testing amplifier power supply.
• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 14 / 17

Phase Lock with Delay Line Control

Building a general purpose phase lock that will tracking with energy ramp Additionally adding control of Colby delay for added flexibility and potential for automated timing

Injection Fiducial USB Interface

Feedback Demonstration System

DAC 400 MHz

D3 D2 Amps DX = Colby Delay lines

RS-232 D2 Control RS-232 D3 control 200MHz locked to SPS signal

Phase Lock + Delay Control Micro- control ler Analog Phase Lock

Revolution Fiducial

Harmonic Multiplier Pickups

SPS 200 MHz 1.6 GHz

Block diagram of phase lock system components.

Injection Fiducial USB Interface DAC 400 MHz RS-232 D2 Control RS-232 D3 control 200MHz locked to SPS signal to Harmonic Multiplier

Phase Lock + Delay Control

Revolution Fiducial SPS 200 MHz x2 Freq Phase Shifter Lo RF LPF ~10MHz Analog Circuitry DC phase

• ffset

IF Microcontroller or front panel control of edge on which to

• lock. Front panel also displays

whether lock is active and whether it is currently locked.

Microcontroller

At injection fiducial begins counting revolutions and adjusting delays at predetermined rate based on number of turns. Interfaces with computer via USB and colby delays via RS-232.

Diagram of phase lock procedure.

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 15 / 17

Upgrades to Feedback Demonstrator System

Implement synchronization for full 4GS/sec sampling rate Additional software for control interface Additional software for data analysis Software for feedback/control specification and filter design Allow for individually configurable coefficients for each slice sample in the FIR Multi-bunch control up to one full batch or possibly more DC offset removal Extended snapshot memory

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 16 / 17

Thank You!

Thank you to the many additional people involved in this project!

CERN: W. Hofle, U. Wehrle, H. Bartosik, G. Kotzian, K. Li, and R. Secondo LBL: A. Ratti, S. De Santis, H. Qian, and Z. Paret LNF: A. Drago, A. Gallo, D. Alesini, F. Marcellini, and M. Zobov SLAC behind-the-scenes: J. Olson and C. Yee KEK: M. Tobiyama

• K. Pollock (SLAC)

Feedback System HW/SW Summary April 9, 2013 17 / 17