Factorizing the Work - Towards a Technical Proposal David Cussans - - PowerPoint PPT Presentation

Factorizing the Work

• Towards a Technical Proposal

David Cussans DAQ Hardware and Interfaces Working Group 26th October 2017

Introduction

• Define and Document interfaces to SP and DP sub detectors

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Where no currently agreed interface exists, work to define one — e.g. TPC readout

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This discussion has started, but let us concentrate on the DAQ side of the interface

• Research and document unit costs for hardware components

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FPGAs, links, memory, boards / crates / power / cooling, network equipment

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Lead to the initial system costing in Technical Proposal ( early ) 2018

• Explore suitable modularity of DAQ hardware

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How many boards, where, how much power, how many links → informed by architecture options

David Cussans | DAQ Hardware & Interfaces WG 2

Introduction

• We now have some “straw man” architectures.
• How do we move towards the DAQ Technical Report?
• How do we distribute the work?
• One group per architecture?
• E.g. SLAC with RCE-like architecture , Columbia/Nevis with Deep

learning approach

• Advantage – greater coherency within each concept.
• Disadvantage – difficult to keep details of benchmark the

same and compare like-with-like ?

• Different groups investigate different aspects.
• E.g. FPGA vs. GPU, memory bandwidth, network
• …. Or combine both approaches.

David Cussans | DAQ Hardware & Interfaces WG 3

Factorizing the work

FPGA Questions

• Compression algorithms
• Started by J.J. Russell, SLAC
• Noise Filtering
• Compare with GPU approach ( started by Philip Rodrigues )
• Memory bandwidth
• If using latency buffer ( rolling buffer ) to allow trigger decision

what is the maximum I/O rate?

• Sets the limit on the number of channels per FPGA ?
• FPGA resources needed for filtering and compression?
• Build on existing work.

David Cussans | DAQ Hardware & Interfaces WG 5

GPU Questions

• “Conventional” feature recognition + triggering:
• Total system requirements.
• Deep Learning / image recognition:
• Coping with “moving picture” rather than static images.
• Triggering?
• Quantifying systematic uncertainties.

David Cussans | DAQ Hardware & Interfaces WG 6

“System Level”

• Optimum size FPGA
• Links: Very simple WIB has just electrical to optical converters.
• (preferred by Cold Electronics)
• Formatting onto 10GBit/s links happens off detector.
• Cost?
• Optimum number of input channels per board?
• Babak Ali showed “straw man” with 8 channels of 1 Gbit/s on a

small board.

• Correlated with I/O to buffer memory
• … if using trigger latency rolling buffer

David Cussans | DAQ Hardware & Interfaces WG 7

Buffer Memory

• What are the implications of a trigger latency buffer?
• 5ms, 1s , 10s ?
• Long buffer for SN triggers?
• Record O(100s) of losslessly compressed data for a SN

trigger.

• Feasible?
• Trivial exercise assuming “MMC” modules.
• 9.2 TB/s from one SP TPC, compression factor 2
• 150s buffer. ~ 20k flash memory modules (bandwidth). ~

US$ 1M

David Cussans | DAQ Hardware & Interfaces WG 8

Summary

• Need to provide raw ingredients for Technical Proposal
• Need to enable new groups to contribute
• → Factorize a few “straw men” designs and evaluate the

individual pieces ( processing, algorithms, I/O , …. )

• See you in NYC

David Cussans | DAQ General Meeting 9