Enhanced Verification by Temporal Decomposition Mike Case , Hari - - PowerPoint PPT Presentation

enhanced verification by temporal decomposition
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Enhanced Verification by Temporal Decomposition Mike Case , Hari - - PowerPoint PPT Presentation

Enhanced Verification by Temporal Decomposition Mike Case , Hari Mony, Jason Baumgartner, Bob Kanzelman FMCAD 2009, Nov. 16, 2009 Introduction Domain: gate-level property checking (and SEC) Problem: simplify the design; remove irrelevant


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Enhanced Verification by Temporal Decomposition

Mike Case, Hari Mony, Jason Baumgartner, Bob Kanzelman FMCAD 2009, Nov. 16, 2009

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Introduction

Domain: gate-level property checking (and SEC) Problem: simplify the design; remove irrelevant detail

[XKCD]

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Outline

Transient Signals – What are they and where do they come from? – How to eliminate them Initialization Inputs – What are they and where do they come from? – How to eliminate them Experimental Results

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Outline

Transient Signals – What are they and where do they come from? – How to eliminate them Initialization Inputs – What are they and where do they come from? – How to eliminate them Experimental Results

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Transient Signals

Definition: a transient signal takes arbitrary values for a finite number

  • f clock cycles and then assumes a fixed constant value

1 1 1 1 1 Register A Register B Register C

Time

1 2 3 4 5

Transient

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Why Do They Occur? – Initialization Sequences

1 1

Pulsed Reset

Register A Register B

Time

1 2 3 4 5

1 1 1 Register C

Transient Transient Transient

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Why Do They Occur? – Verification Testbenches

Testbench all FPU signals are transient

MUL NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP MUL MUL MUL

Design Under Test Driver Checker

Testbench FPU Pipeline Time 0: Time 1: Time 2: Time 3: Time >3:

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How Common Are Transient Signals?

On 105 “hard” IBM designs: 49% had transients On 27 “hard” HWMCC designs: 25% had transients

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Outline

Transient Signals – What are they and where do they come from? – How to eliminate them Initialization Inputs – What are they and where do they come from? – How to eliminate them Experimental Results

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Time 3: State=X0XX, Inputs=XX Time 2: State=X00X, Inputs=XX

Detecting Transients With Ternary Simulation

Time 4: State=X00X, Inputs=XX Time 0: State=0000, Inputs=XX Time 1: State=0X1X, Inputs=XX Transient Ternary Sim. Execution Abstract State Space Fast, but incomplete

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Temporal Decomposition For Verification

Time

1 2 3 4 5

Maximum Transient Duration

Definition: the transient duration is the number of time steps before a transient settles to its constant value

Check with BMC Check with unbounded model checking

1 Register C

Time

1 2 3 4 5

Transient with duration 2

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Time Shifting for Unbounded Verification

Registers Initial Values init1 init2 inp. Next States Prop. Initial Values Transition Relation Transition Relation init1 init2 inp3 inp2 N Simplify Transient Signals Transition Relation Prop. inp1 Transition Relation

Modeling: a register’s initial values is an arbitrary combinational function New design starts in any state reachable in N steps.

  • Max. Transient

Duration

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Simplification Results

Resources limit the transients that can be simplified TR decreases Initialization logic increases

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Outline

Transient Signals – What are they and where do they come from? – How to eliminate them Initialization Inputs – What are they and where do they come from? – How to eliminate them Experimental Results

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We have lots of initialization inputs

Registers Initial Values input Next States Prop. Transition Relation input input input input Initialization Inputs

Definition: an initialization input is a primary input that is only needed to compute the initial state

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Transient Simplification Creates Initialization Inputs

We created initialization inputs!

Prop. Transition Relation Transition Relation init1 init2 inp3 inp2 inp1 Transition Relation

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Outline

Transient Signals – What are they and where do they come from? – How to eliminate them Initialization Inputs – What are they and where do they come from? – How to eliminate them Experimental Results

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Definition: a signal X is observable at signal Y if a toggle at X can cause a toggle at Y – Approximate with structural analysis Simplify initialization inputs that are never observable at any property

Initialization and Observability

Registers Initial Values input Next States Prop. Transition Relation input input input input Unchanged (might change) (might change)

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Simplification of Initialization Inputs: High Level

No initialization inputs observable at Prop0 Two initialization inputs un-observable at Next0 Un-observable at Propj ∀ j > 0

input input

TR

Prop. Next states Curr states primary inputs input input input Frame 0 Registers Initial Values input Next States Prop. Transition Relation input input input input

BMC

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TR

Prop. Next states Curr states primary inputs Frame 1 input

Simplification of Initialization Inputs: High Level

TR

Prop. Next states Curr states primary inputs input input input Frame 0 Registers Initial Values input Next States Prop. Transition Relation input input

BMC

No initialization inputs observable at Prop0 Initialization inputs maybe observable at Next1 Maybe observable at Propj ∀ j > 1

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Simplification Results

Fast, but incomplete

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Outline

Transient Signals – What are they and where do they come from? – How to eliminate them Initialization Inputs – What are they and where do they come from? – How to eliminate them Experimental Results

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Runtime of our Methods + BMC Results

Two methods presented: – Transient Simplification – Runtime capped at 10 seconds – Initialization Input Simplification – Runtime capped at 10 seconds Tested on 105 “hard” industrial designs and 27 “hard” academic designs – Largest was 632K ands and 97K registers

Note: this is a systematic improvement on a large benchmark suite, not a collection of anecdotal examples

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Synthesis Results

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Verification Results

Induction results: – Transient logic often breaks induction – Our methods can render problems inductive

  • Design 1: 22k Ands and 800 registers, solvable in 42 sec
  • Design 2: 20k Ands and 3k registers, solvable in 56 sec
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Conclusion

Transient and Initialization Input Simplification Fast running Benefits synthesis and verification

Thank You