Embedding Crypto in SoCs: Threats and Protections Arnaud Tisserand - - PowerPoint PPT Presentation

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Embedding Crypto in SoCs: Threats and Protections Arnaud Tisserand - - PowerPoint PPT Presentation

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Embedding Crypto in SoCs: Threats and Protections Arnaud Tisserand CNRS, Lab-STICC laboratory GDR SoC17, Bordeaux Summary Introduction & Cryptographic Background Side Channel Attacks Fault Injection Attacks Protections

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SLIDE 1

Embedding Crypto in SoCs: Threats and Protections

Arnaud Tisserand

CNRS, Lab-STICC laboratory

GDR SoC’17, Bordeaux

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SLIDE 2

Summary

  • Introduction & Cryptographic Background
  • Side Channel Attacks
  • Fault Injection Attacks
  • Protections Examples
  • Conclusion and References

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 2/62

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SLIDE 3

Applications with Security Needs

Applications: smart cards, computers, Internet, telecommunications, set-top boxes, data storage, RFID tags, WSN, smart grids. . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 3/62

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SLIDE 4

Cryptographic Features

Objectives:

  • Confidentiality
  • Integrity
  • Authenticity
  • Non-repudiation
  • . . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 4/62

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SLIDE 5

Cryptographic Features

Objectives:

  • Confidentiality
  • Integrity
  • Authenticity
  • Non-repudiation
  • . . .

Cryptographic primitives:

  • Encryption
  • Digital signature
  • Hash function
  • Random numbers generation
  • . . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 4/62

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SLIDE 6

Cryptographic Features

Objectives:

  • Confidentiality
  • Integrity
  • Authenticity
  • Non-repudiation
  • . . .

Cryptographic primitives:

  • Encryption
  • Digital signature
  • Hash function
  • Random numbers generation
  • . . .

Implementation issues:

  • Performances: speed, delay, throughput, latency
  • Cost: device (memory, size, weight), low power/energy consumption,

design

  • Security: protection against attacks

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 4/62

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SLIDE 7

Symmetric / Private-Key Cryptography

A B M

  • A : Alice, B : Bob
  • M: plain text/message

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 5/62

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SLIDE 8

Symmetric / Private-Key Cryptography

A B M E D

  • A : Alice, B : Bob
  • M: plain text/message
  • E: encryption/ciphering algorithm, D: decryption/deciphering

algorithm

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 5/62

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SLIDE 9

Symmetric / Private-Key Cryptography

A B M E D k Ek(M)

  • A : Alice, B : Bob
  • M: plain text/message
  • E: encryption/ciphering algorithm, D: decryption/deciphering

algorithm

  • k: secret key
  • Ek(M): encrypted text

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 5/62

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SLIDE 10

Symmetric / Private-Key Cryptography

A B M E D k Ek(M) k Dk(Ek(M)) = M

  • A : Alice, B : Bob
  • M: plain text/message
  • E: encryption/ciphering algorithm, D: decryption/deciphering

algorithm

  • k: secret key to be shared by A and B
  • Ek(M): encrypted text
  • Dk(Ek(M)): decrypted text

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 5/62

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SLIDE 11

Symmetric / Private-Key Cryptography

A B M E D k Ek(M) k Dk(Ek(M)) = M E

  • A : Alice, B : Bob
  • M: plain text/message
  • E: encryption/ciphering algorithm, D: decryption/deciphering

algorithm

  • k: secret key to be shared by A and B
  • Ek(M): encrypted text
  • Dk(Ek(M)): decrypted text
  • E : eavesdropper/spy

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 5/62

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SLIDE 12

Advanced Encryption Standard (AES)

Established by NIST in 2001 Symmetric encryption Block size: 128 bits key length #round 128 10 192 12 256 14 Based on substitution- permutation network

Image source: http://fr.wikipedia.org/ NIST: National Institute of Standards and Technology

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 6/62

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SLIDE 13

AES Round Operations

Images source: http://fr.wikipedia.org/

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 7/62

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SLIDE 14

Asymmetric / Public-Key Cryptography

A B M E D E

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 8/62

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SLIDE 15

Asymmetric / Public-Key Cryptography

A B M E D k Ek(M) k E

  • k: B’s public key (known to everyone including E)
  • Ek(M): ciphered text

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 8/62

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SLIDE 16

Asymmetric / Public-Key Cryptography

A B M E D k Ek(M) k k′ Dk′(Ek(M)) = M E

  • k: B’s public key (known to everyone including E)
  • Ek(M): ciphered text
  • k′: B’s private key (must be kept secret)
  • Dk′(Ek(M)): deciphered text

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 8/62

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SLIDE 17

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 18

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

  • Choose two large prime integers p and q

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 19

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

  • Choose two large prime integers p and q
  • Compute the modulus n = pq

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 20

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

  • Choose two large prime integers p and q
  • Compute the modulus n = pq
  • Compute ϕ(n) = (p − 1)(q − 1)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 21

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

  • Choose two large prime integers p and q
  • Compute the modulus n = pq
  • Compute ϕ(n) = (p − 1)(q − 1)
  • Choose an integer e such that 1 < e < ϕ(n) and gcd(e, ϕ(n)) = 1

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 22

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

  • Choose two large prime integers p and q
  • Compute the modulus n = pq
  • Compute ϕ(n) = (p − 1)(q − 1)
  • Choose an integer e such that 1 < e < ϕ(n) and gcd(e, ϕ(n)) = 1
  • Compute d = e−1 mod ϕ(n)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 23

RSA Asymmetric Cryptosystem (1/2)

Published in 1978 by Ron Rivest, Adi Shamir and Leonard Adleman [17] Key generation (Alice side)

  • Choose two large prime integers p and q
  • Compute the modulus n = pq
  • Compute ϕ(n) = (p − 1)(q − 1)
  • Choose an integer e such that 1 < e < ϕ(n) and gcd(e, ϕ(n)) = 1
  • Compute d = e−1 mod ϕ(n)
  • Private key (kept secret by Alice): d

and also p, q, ϕ(n)

  • Public key (published): (n, e)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 9/62

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SLIDE 24

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 25

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 26

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

  • convert the message M to an integer m

(1 < m < n and gcd(m, n) = 1)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 27

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

  • convert the message M to an integer m

(1 < m < n and gcd(m, n) = 1)

  • compute the cipher text c = me mod n

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 28

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

  • convert the message M to an integer m

(1 < m < n and gcd(m, n) = 1)

  • compute the cipher text c = me mod n

Decryption (Alice side):

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 29

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

  • convert the message M to an integer m

(1 < m < n and gcd(m, n) = 1)

  • compute the cipher text c = me mod n

Decryption (Alice side):

  • compute m = cd mod n

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 30

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

  • convert the message M to an integer m

(1 < m < n and gcd(m, n) = 1)

  • compute the cipher text c = me mod n

Decryption (Alice side):

  • compute m = cd mod n
  • convert the integer m to the message M

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 31

RSA Asymmetric Cryptosystem (2/2)

Private key (Alice): d Public key (all): (n, e) Encryption (Bob side):

  • convert the message M to an integer m

(1 < m < n and gcd(m, n) = 1)

  • compute the cipher text c = me mod n

Decryption (Alice side):

  • compute m = cd mod n
  • convert the integer m to the message M

Theoretical security: integer factorization, i.e. computing (p, q) knowing n, is not possible when n is large enough

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62

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SLIDE 32

Modular Exponentiation

Computation of operations such as : ab mod n ab = a × a × a × a × . . . × a × a × a

  • a appears b times

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 11/62

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SLIDE 33

Modular Exponentiation

Computation of operations such as : ab mod n ab = a × a × a × a × . . . × a × a × a

  • a appears b times

Order of magnitude of exponents: 2size of exponent 21024 . . . 22048 . . . 24096

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 11/62

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SLIDE 34

Modular Exponentiation

Computation of operations such as : ab mod n ab = a × a × a × a × . . . × a × a × a

  • a appears b times

Order of magnitude of exponents: 2size of exponent 21024 . . . 22048 . . . 24096 Fast exponentiation principle: ab = (a2)

b 2

when b is even = a × (a2)

b−1 2

when b is odd Least significant bit of the exponent: bit = 0 even and bit = 1 odd

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 11/62

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SLIDE 35

Square and Multiply Algorithm

input : a , b , n where b = (bt−1bt−2 . . . b1b0)2

  • utput : ab mod n

r = 1 for i from 0 to t − 1 do i f bi = 1 then r = r · a mod n endif a = a2 mod n endfor return r This is the right to left version (there exists a left to right one)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 12/62

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SLIDE 36

Hardware Accelerators for Elliptic Curve Crypto.

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

P + P curve level

x±y x×y . . .

field level

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62

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SLIDE 37

Hardware Accelerators for Elliptic Curve Crypto.

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

P + P curve level

x±y x×y . . .

field level

E : y 2 = x3 + 4x + 20 over GF(1009) points: P, Q= (x, y) or (x, y, z) or . . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62

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SLIDE 38

Hardware Accelerators for Elliptic Curve Crypto.

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

P + P curve level

x±y x×y . . .

field level

E : y 2 = x3 + 4x + 20 over GF(1009) points: P, Q= (x, y) or (x, y, z) or . . . coordinates: x, y, z ∈ GF(·) GF(p), GF(2m), t : 200–600 bits k = (kt−1kt−2 . . . k1k0)2 ∈ N

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62

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SLIDE 39

Hardware Accelerators for Elliptic Curve Crypto.

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

P + P curve level

x±y x×y . . .

field level

E : y 2 = x3 + 4x + 20 over GF(1009) points: P, Q= (x, y) or (x, y, z) or . . . coordinates: x, y, z ∈ GF(·) GF(p), GF(2m), t : 200–600 bits k = (kt−1kt−2 . . . k1k0)2 ∈ N Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62

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SLIDE 40

Hardware Accelerators for Elliptic Curve Crypto.

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

P + P curve level

x±y x×y . . .

field level

E : y 2 = x3 + 4x + 20 over GF(1009) points: P, Q= (x, y) or (x, y, z) or . . . coordinates: x, y, z ∈ GF(·) GF(p), GF(2m), t : 200–600 bits k = (kt−1kt−2 . . . k1k0)2 ∈ N Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P) Point addition/doubling operations sequence of finite field operations DBL: v1 = z2

1, v2 = x1 − v1, . . .

ADD: w1 = z2

1, w2 = z1 × w1, . . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62

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SLIDE 41

Hardware Accelerators for Elliptic Curve Crypto.

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

P + P curve level

x±y x×y . . .

field level

E : y 2 = x3 + 4x + 20 over GF(1009) points: P, Q= (x, y) or (x, y, z) or . . . coordinates: x, y, z ∈ GF(·) GF(p), GF(2m), t : 200–600 bits k = (kt−1kt−2 . . . k1k0)2 ∈ N Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P) Point addition/doubling operations sequence of finite field operations DBL: v1 = z2

1, v2 = x1 − v1, . . .

ADD: w1 = z2

1, w2 = z1 × w1, . . .

GF(p) or GF(2m) operations

  • peration modulo large prime (GF(p))
  • r irreducible polynomial (GF(2m))

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62

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SLIDE 42

Attacks

attack

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62

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SLIDE 43

Attacks

attack

  • bservation

perturbation invasive

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62

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SLIDE 44

Attacks

attack

  • bservation

perturbation invasive timing analysis power analysis EMR analysis fault injection probing reverse engineering EMR = Electromagnetic radiation

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62

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SLIDE 45

Attacks

attack

  • bservation

perturbation invasive timing analysis power analysis EMR analysis fault injection probing reverse engineering theoretical EMR = Electromagnetic radiation

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62

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SLIDE 46

Attacks

attack

  • bservation

perturbation invasive timing analysis power analysis EMR analysis fault injection probing reverse engineering theoretical advanced algorithms

  • ptimized programming

EMR = Electromagnetic radiation

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62

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SLIDE 47

Side Channel Attacks (SCAs) (1/2)

Attack: attempt to find, without any knowledge about the secret:

  • the message (or parts of the message)
  • informations on the message
  • the secret (or parts of the secret)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 15/62

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SLIDE 48

Side Channel Attacks (SCAs) (1/2)

Attack: attempt to find, without any knowledge about the secret:

  • the message (or parts of the message)
  • informations on the message
  • the secret (or parts of the secret)

“Old style” side channel attacks:

+

clic clac good value bad value

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 15/62

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SLIDE 49

Side Channel Attacks (SCAs) (2/2)

A B E D M k Ek(M) k Dk(Ek(M)) = M General principle: measure external parameter(s) on running device in

  • rder to deduce internal informations

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 16/62

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SLIDE 50

Side Channel Attacks (SCAs) (2/2)

A B E D M k Ek(M) k Dk(Ek(M)) = M E measure k, M??? attack General principle: measure external parameter(s) on running device in

  • rder to deduce internal informations

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 16/62

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SLIDE 51

What Should be Measured?

Answer: everything that can “enter” and/or “get out” in/from the device

  • power consumption
  • electromagnetic radiation
  • temperature
  • sound
  • computation time
  • number of cache misses
  • number and type of error messages
  • ...

The measured parameters may provide informations on:

  • global behavior (temperature, power, sound...)
  • local behavior (EMR, # cache misses...)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 17/62

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SLIDE 52

Power Consumption Analysis

General principle:

  • 1. measure the current i(t) in the cryptosystem
  • 2. use those measurements to “deduce” secret informations

VDD

i(t) crypto.

R

traces

secret key = 962571. . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 18/62

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SLIDE 53

Simple Power Analysis (SPA)

Source: [11]

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 19/62

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SLIDE 54

Simple Power Analysis (SPA)

Source: [11]

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 19/62

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SLIDE 55

Limits of the SPA

Example of behavior difference: (activity into a register) t t + 1 0000000000000000 0000000000000000

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62

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SLIDE 56

Limits of the SPA

Example of behavior difference: (activity into a register) t t + 1 0000000000000000 0000000000000000 1111111111111111 0000000000000001

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62

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SLIDE 57

Limits of the SPA

Example of behavior difference: (activity into a register) t t + 1 0000000000000000 0000000000000000 1111111111111111 0000000000000001 Important: a small difference may be evaluated has a noise during the measurement traces cannot be distinguished Question: what can be done when differences are too small?

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62

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SLIDE 58

Limits of the SPA

Example of behavior difference: (activity into a register) t t + 1 0000000000000000 0000000000000000 1111111111111111 0000000000000001 Important: a small difference may be evaluated has a noise during the measurement traces cannot be distinguished Question: what can be done when differences are too small? Answer: use statistics over several traces

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62

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SLIDE 59

Differential Power Analysis (DPA)

cryptosystem

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 60

Differential Power Analysis (DPA)

cryptosystem internal state

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 61

Differential Power Analysis (DPA)

cryptosystem internal state select bit b to attack b = 1 b = 0

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 62

Differential Power Analysis (DPA)

cryptosystem internal state select bit b to attack b = 1 b = 0 implementation

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 63

Differential Power Analysis (DPA)

cryptosystem internal state select bit b to attack b = 1 b = 0 implementation power model

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 64

Differential Power Analysis (DPA)

cryptosystem internal state select bit b to attack b = 1 b = 0 implementation power model power(Hb=1) power(Hb=0)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 65

Differential Power Analysis (DPA)

cryptosystem internal state select bit b to attack b = 1 b = 0 implementation power model power(Hb=1) power(Hb=0) measures

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 66

Differential Power Analysis (DPA)

cryptosystem internal state select bit b to attack b = 1 b = 0 implementation power model power(Hb=1) power(Hb=0) measures comparison correct hypothesis

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62

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SLIDE 67

Template Attack

cryptosystem

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62

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SLIDE 68

Template Attack

cryptosystem internal state

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62

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SLIDE 69

Template Attack

cryptosystem internal state select variable v to attack v = 0 v = 1 v = 2

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62

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SLIDE 70

Template Attack

cryptosystem internal state select variable v to attack v = 0 v = 1 v = 2 implementation

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62

slide-71
SLIDE 71

Template Attack

cryptosystem internal state select variable v to attack v = 0 v = 1 v = 2 implementation measures power(v = 0) power(v = 1) power(v = 2) training step

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62

slide-72
SLIDE 72

Template Attack

cryptosystem internal state select variable v to attack v = 0 v = 1 v = 2 implementation measures power(v = 0) power(v = 1) power(v = 2) training step measures

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slide-73
SLIDE 73

Template Attack

cryptosystem internal state select variable v to attack v = 0 v = 1 v = 2 implementation measures power(v = 0) power(v = 1) power(v = 2) training step measures comparison correct hypothesis

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slide-74
SLIDE 74

Electromagnetic Radiation Analysis

General principle: use a probe to measure the EMR circuit VDD GND EMR measurement:

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 23/62

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SLIDE 75

Electromagnetic Radiation Analysis

General principle: use a probe to measure the EMR circuit VDD GND EMR measurement:

  • global EMR with a large probe

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SLIDE 76

Electromagnetic Radiation Analysis

General principle: use a probe to measure the EMR circuit VDD GND EMR measurement:

  • global EMR with a large probe
  • local EMR with a micro-probe

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SLIDE 77

Side Channel Attack on ECC

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

curve level

x±y x×y . . .

field level

Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

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slide-78
SLIDE 78

Side Channel Attack on ECC

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

curve level

x±y x×y . . .

field level

Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

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slide-79
SLIDE 79

Side Channel Attack on ECC

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

curve level

x±y x×y . . .

field level

DBL DBL DBL DBL DBL DBL

Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

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slide-80
SLIDE 80

Side Channel Attack on ECC

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

curve level

x±y x×y . . .

field level

DBL DBL DBL DBL DBL DBL ADD ADD

Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

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slide-81
SLIDE 81

Side Channel Attack on ECC

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

curve level

x±y x×y . . .

field level

DBL DBL DBL DBL DBL DBL ADD ADD

0 0 0 1 1

Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

  • simple power analysis (& variants)

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SLIDE 82

Side Channel Attack on ECC

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P)

curve level

x±y x×y . . .

field level

DBL DBL DBL DBL DBL DBL ADD ADD

0 0 0 1 1

Scalar multiplication operation for i from 0 to t − 1 do if ki = 1 then Q = ADD(P, Q) P = DBL(P)

  • simple power analysis (& variants)
  • differential power analysis (& variants)
  • horizontal/vertical/templates/. . . attacks

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SLIDE 83

Fault Injection Attacks

Objective: alter the correct functioning of a system “from outside” Fault effects examples:

  • modify a value in a register
  • modify a value in the memory hierarchy
  • modify an address (data location or code location)
  • modify a control signal (e.g. status flag, branch direction)
  • skip/modify the instruction decoding
  • delay/advance propagation of internal control signals
  • etc.

Also called perturbation attacks

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SLIDE 84

Fault Injection Techniques

Typical techniques:

  • perturbation in the power supply voltage
  • perturbation of the clock signal
  • temperature (over/under-heating the chip)
  • radiation or electromagnetic (EM) disturbances
  • exposing the chip to intense lights or beams
  • etc

Accuracy:

  • time: part of clock cycle, clock cycle, code block (instruction sequence)
  • space: gate, block, unit, core, chip, package
  • value: set to a specific value, bit flip, stuck-at 0 or 1, random

modification

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SLIDE 85

Perturbation on the Power Supply

Principle: controlled power supply time voltage

  • Nominal power supply (e.g. ≈ [0.7, 1.2] V for current technologies)

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SLIDE 86

Perturbation on the Power Supply

Principle: controlled power supply device under attack VDD GND time voltage

  • Nominal power supply (e.g. ≈ [0.7, 1.2] V for current technologies)
  • Non-nominal constant power supply (e.g. 0.7 V instead of 1.2 V)

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SLIDE 87

Perturbation on the Power Supply

Principle: controlled power supply device under attack device under attack power glitch generator VDD GND time voltage

  • Nominal power supply (e.g. ≈ [0.7, 1.2] V for current technologies)
  • Non-nominal constant power supply (e.g. 0.7 V instead of 1.2 V)
  • Glitches (dips, spikes) in the power supply at some selected moments

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SLIDE 88

Under Powering Example

Source: paper [19] presented at EDCC 2008 conference Setup: 130 nm smart card (1.2 V nominal VDD) with AES crypto-processor Measurement campaign: triples (msg, key, cypher) recorded for 100 VDD in [775, 825] mV over 20,000 encryptions with comparison to a (RTL) simulation for one byte corruption in the state matrix at various rounds

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SLIDE 89

Under Powering Example

Source: paper [19] presented at EDCC 2008 conference Setup: 130 nm smart card (1.2 V nominal VDD) with AES crypto-processor Measurement campaign: triples (msg, key, cypher) recorded for 100 VDD in [775, 825] mV over 20,000 encryptions with comparison to a (RTL) simulation for one byte corruption in the state matrix at various rounds Observed behavior is compatible with setup violation model on a critical path (bell shape due to only one or multiple paths)

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SLIDE 90

Under Powering Example

Source: paper [19] presented at EDCC 2008 conference Setup: 130 nm smart card (1.2 V nominal VDD) with AES crypto-processor Measurement campaign: triples (msg, key, cypher) recorded for 100 VDD in [775, 825] mV over 20,000 encryptions with comparison to a (RTL) simulation for one byte corruption in the state matrix at various rounds Observed behavior is compatible with setup violation model on a critical path (bell shape due to only one or multiple paths)

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SLIDE 91

Power Glitching Example

Source: FDTC 2008 conference paper [18] Setup: AVR microcontroller with RSA implementation Attack result: a power glitch causes to skip some instruction

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SLIDE 92

Perturbation on the External Clock

Principle: time voltage CLK

  • Normal clock (at a given frequency, duty cycle ≈ 50%)

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SLIDE 93

Perturbation on the External Clock

Principle: time voltage CLK MCLK

  • Normal clock (at a given frequency, duty cycle ≈ 50%)
  • Clock with a modified duty cycle

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SLIDE 94

Perturbation on the External Clock

Principle: time voltage CLK MCLK GCLK glitches

  • Normal clock (at a given frequency, duty cycle ≈ 50%)
  • Clock with a modified duty cycle
  • Glitched clock
  • Etc.

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SLIDE 95

Glitchy Clock Generation Example

Source: paper [10] published in J. Crypto. Eng. 2011 Setup: Virtex-II Pro FPGA (on SASEBO card) used to generate a “glitchy” clock for several programmable time parameters

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SLIDE 96

Clock Glitch Attack Example

Source: paper [1] presented at FDTC 2011 conference Setup: AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

NOP 0000 0000 0000 0000 normal

  • i + 1

EOR R15,R5 0010 0100 1111 0101

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SLIDE 97

Clock Glitch Attack Example

Source: paper [1] presented at FDTC 2011 conference Setup: AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

NOP 0000 0000 0000 0000 normal

  • i + 1

EOR R15,R5 0010 0100 1111 0101 glitch 59 ns i + 1 NOP 0000 0000 0000 0000

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SLIDE 98

Clock Glitch Attack Example

Source: paper [1] presented at FDTC 2011 conference Setup: AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

NOP 0000 0000 0000 0000 normal

  • i + 1

EOR R15,R5 0010 0100 1111 0101 glitch 59 ns i + 1 NOP 0000 0000 0000 0000 mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

NOP 0000 0000 0000 0000 normal

  • i + 1

SER R18 1110 1111 0010 1111

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SLIDE 99

Clock Glitch Attack Example

Source: paper [1] presented at FDTC 2011 conference Setup: AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

NOP 0000 0000 0000 0000 normal

  • i + 1

EOR R15,R5 0010 0100 1111 0101 glitch 59 ns i + 1 NOP 0000 0000 0000 0000 mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

NOP 0000 0000 0000 0000 normal

  • i + 1

SER R18 1110 1111 0010 1111 glitch 61 ns i + 1 LDI R18,0xEF 1110 1110 0010 1111 glitch 60 ns i + 1 SBC R12,R15 0000 1000 0010 1111 glitch 59 ns i + 1 NOP 0000 0000 0000 0000

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SLIDE 100

mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

TST R12 0010 0000 1100 1100 normal

  • i + 1

BREQ PC+0x02 1111 0000 0000 1001 normal

  • i + 2

SER R26 1110 1111 1010 1111

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SLIDE 101

mode glitch period cycle instruction

  • pcode (bin)

normal

  • i

TST R12 0010 0000 1100 1100 normal

  • i + 1

BREQ PC+0x02 1111 0000 0000 1001 normal

  • i + 2

SER R26 1110 1111 1010 1111 glitch 57 ns i + 2 LDI R26,0xEF 1110 1110 1010 1111 glitch 56 ns i + 2 LDI R26,0xCF 1110 1100 1010 1111 glitch 52 ns i + 2 LDI R26,0x0F 1110 0000 1010 1111 glitch 45 ns i + 2 LDI R16,0x09 1110 0000 0000 1001 glitch 32 ns i + 2 LD R0,Y+0x01 1000 0000 0000 1001 glitch 28 ns i + 2 LD R9,Y 1000 0000 0000 1000 glitch 27 ns i + 2 LDI R16,0x09 1110 0000 0000 1001 glitch 15 ns i + 2 BREQ PC+0x02 1111 0000 0000 1001

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SLIDE 102

Electromagnetic Perturbations

Principle: circuit pulse gen- erator

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 34/62

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SLIDE 103

Electromagnetic Perturbations

Principle: circuit pulse gen- erator

  • large antenna

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SLIDE 104

Electromagnetic Perturbations

Principle: circuit pulse gen- erator

  • large antenna
  • micro-antenna

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SLIDE 105

Electromagnetic Perturbations

Principle: circuit pulse gen- erator Y X Z

  • large antenna
  • micro-antenna with motorized (X,Y,Z) stage/table

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SLIDE 106

Electromagnetic Attack Example

Source: article [12] presented at FDTC 2013 conference Setup: 32-b Cortex-M3 ARM microprocessor (CMOS 130 nm SoC at 56 MHz), magnetic antenna with pulses in [-200, 200] V and [10, 200] ns

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SLIDE 107

Loaded value: 12345678 Pulse voltage [V] Loaded value Occurrence rate [%] 170 1234 5678 100 172 1234 5678 100 174 9234 5678 73 176 FE34 5678 30 178 FFF4 5678 53 180 FFFD 5678 50 182 FFFF 7F78 46 184 FFFF FFFB 40 186 FFFF FFFF 100 188 FFFF FFFF 100 190 FFFF FFFF 100

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SLIDE 108

Lights / Lasers

Principle: circuit

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SLIDE 109

Lights / Lasers

Principle: circuit light source

  • large illuminated area (flash light with microscope)

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SLIDE 110

Lights / Lasers

Principle: circuit light source light source

  • large illuminated area (flash light with microscope)
  • small “spot” (laser with variable locations)

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SLIDE 111

Differential Fault Analysis

Most of time, exploiting only one fault does not provide enough information

  • Accurately injecting fault is difficult
  • The fault causes a few perturbations

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SLIDE 112

Differential Fault Analysis

Most of time, exploiting only one fault does not provide enough information

  • Accurately injecting fault is difficult
  • The fault causes a few perturbations

Then, use statistical correlation(s)

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SLIDE 113

Safe Error Attack

Principle: exploit the link (or the lack of link) between injected fault(s) during “useful” (or “useless”) operations and the final result time

  • 1
  • 2
  • 3
  • 4
  • 5

end

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SLIDE 114

Safe Error Attack

Principle: exploit the link (or the lack of link) between injected fault(s) during “useful” (or “useless”) operations and the final result time

  • 1
  • 2
  • 3
  • 4
  • 5

end fault injection

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SLIDE 115

Safe Error Attack

Principle: exploit the link (or the lack of link) between injected fault(s) during “useful” (or “useless”) operations and the final result time

  • 1
  • 2
  • 3
  • 4
  • 5

end fault injection time

  • 1
  • 2
  • 5
  • 3
  • 4

end

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slide-116
SLIDE 116

Safe Error Attack

Principle: exploit the link (or the lack of link) between injected fault(s) during “useful” (or “useless”) operations and the final result time

  • 1
  • 2
  • 3
  • 4
  • 5

end fault injection time

  • 1
  • 2
  • 5
  • 3
  • 4

end fault injection

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SLIDE 117

Safe Error Attack Example in Asymmetric Crypto

for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .)

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SLIDE 118

Safe Error Attack Example in Asymmetric Crypto

for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) WEAK against SPA

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SLIDE 119

Safe Error Attack Example in Asymmetric Crypto

for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) WEAK against SPA for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) else w ← f (v, . . .) v ← g(v, . . .)

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SLIDE 120

Safe Error Attack Example in Asymmetric Crypto

for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) WEAK against SPA for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) else w ← f (v, . . .) v ← g(v, . . .) WEAK against SEA

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SLIDE 121

Safe Error Attack Example in Asymmetric Crypto

for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) WEAK against SPA for i from 0 to n − 1 do if si = 1 then v ← f (v, . . .) v ← g(v, . . .) else w ← f (v, . . .) v ← g(v, . . .) WEAK against SEA Useless or dummy operations are a bad idea

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SLIDE 122

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k

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SLIDE 123

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k M

  • choose a plaintext message M

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SLIDE 124

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k M C = Ek(M)

  • choose a plaintext message M
  • encrypt M into C = Ek(M)

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SLIDE 125

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k M C = Ek(M) flip(di)

  • choose a plaintext message M
  • encrypt M into C = Ek(M)
  • inject a fault by fliping di for a random i (d is the secret key)

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SLIDE 126

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k M C = Ek(M) flip(di) Dk(C) = M

  • choose a plaintext message M
  • encrypt M into C = Ek(M)
  • inject a fault by fliping di for a random i (d is the secret key)
  • compute M

M = c2i di c2i di

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SLIDE 127

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k M C = Ek(M) flip(di) Dk(C) = M

  • choose a plaintext message M
  • encrypt M into C = Ek(M)
  • inject a fault by fliping di for a random i (d is the secret key)
  • compute M

M = c2i di c2i di

  • test:

◮

M M = 1 c2i mod N =

⇒ di = 1

◮

M M = c2i mod N =

⇒ di = 0

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SLIDE 128

Fault Attack Example: Bit Flip on RSA Decryption

A B E D k′ k M C = Ek(M) flip(di) Dk(C) = M

  • choose a plaintext message M
  • encrypt M into C = Ek(M)
  • inject a fault by fliping di for a random i (d is the secret key)
  • compute M

M = c2i di c2i di

  • test:

◮

M M = 1 c2i mod N =

⇒ di = 1

◮

M M = c2i mod N =

⇒ di = 0

  • retry for several i (=

⇒ get small parts of d, then mathematical attacks)

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SLIDE 129

Many other fault attacks. . .

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SLIDE 130

Countermeasures

Principles for preventing attacks:

  • embed additional protection blocks
  • modify the original circuit into a secured version
  • application levels: circuit, architecture, algorithm, protocol. . .

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SLIDE 131

Countermeasures

Principles for preventing attacks:

  • embed additional protection blocks
  • modify the original circuit into a secured version
  • application levels: circuit, architecture, algorithm, protocol. . .

Countermeasures:

  • electrical shielding
  • detectors, estimators, decoupling
  • use uniform computation durations and power consumption
  • use detection/correction codes (for fault injection attacks)
  • provide a random behavior (algorithms, representation, operations. . . )
  • add noise (e.g. masking, useless instructions/computations)
  • circuit reconfiguration (algorithms, block location, representation of
  • values. . . )

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SLIDE 132

Low-Level Coding and Circuit Activity

Assumptions:

  • b is a bit (i.e. b ∈ {0, 1}, logical or mathematical value)
  • electrical states for a wire

: VDD (logical 1) or GND (logical 0)

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SLIDE 133

Low-Level Coding and Circuit Activity

Assumptions:

  • b is a bit (i.e. b ∈ {0, 1}, logical or mathematical value)
  • electrical states for a wire

: VDD (logical 1) or GND (logical 0) Low-level codings of a bit: b = 0 b = 1 standard GND VDD

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SLIDE 134

Low-Level Coding and Circuit Activity

Assumptions:

  • b is a bit (i.e. b ∈ {0, 1}, logical or mathematical value)
  • electrical states for a wire

: VDD (logical 1) or GND (logical 0) Low-level codings of a bit: b = 0 b = 1 standard GND VDD dual rail r0 =VDD r1 =GND (1, 0)DR r0 =GND r1 =VDD (0, 1)DR

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SLIDE 135

Low-Level Coding and Circuit Activity

Assumptions:

  • b is a bit (i.e. b ∈ {0, 1}, logical or mathematical value)
  • electrical states for a wire

: VDD (logical 1) or GND (logical 0) Low-level codings of a bit: b = 0 b = 1 standard GND VDD dual rail r0 =VDD r1 =GND (1, 0)DR r0 =GND r1 =VDD (0, 1)DR

cycles b r0 r1

slide-136
SLIDE 136

Low-Level Coding and Circuit Activity

Assumptions:

  • b is a bit (i.e. b ∈ {0, 1}, logical or mathematical value)
  • electrical states for a wire

: VDD (logical 1) or GND (logical 0) Low-level codings of a bit: b = 0 b = 1 standard GND VDD dual rail r0 =VDD r1 =GND (1, 0)DR r0 =GND r1 =VDD (0, 1)DR

cycles b r0 r1

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 44/62

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SLIDE 137

Circuit Logic Styles

Countermeasure principles: uniformize circuit activity and exclusive coding

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 45/62

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SLIDE 138

Circuit Logic Styles

Countermeasure principles: uniformize circuit activity and exclusive coding Solution based on precharge logic and dual-rail coding:

cycles pc r0 r1

evaluation b = 0 precharge invalid evaluation b = 0 precharge invalid evaluation b = 1 precharge invalid

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 45/62

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SLIDE 139

Circuit Logic Styles

Countermeasure principles: uniformize circuit activity and exclusive coding Solution based on precharge logic and dual-rail coding:

cycles pc r0 r1

evaluation b = 0 precharge invalid evaluation b = 0 precharge invalid evaluation b = 1 precharge invalid

Solution based on validity line and dual-rail coding: r1 r0 valid Important overhead: silicon area and local storage (registers)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 45/62

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SLIDE 140

Circuit-Level Protections for Arithmetic Operators

References: [8] and [9]

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 46/62

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SLIDE 141

Countermeasure: Architecture

Increase internal parallelism:

  • replace one fast but big operator
  • by several instances of a small but slow one
  • archi. A
  • p
  • archi. B
  • p1
  • p2
  • p3
  • p4

time

  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p
  • p

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 47/62

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SLIDE 142

Protected Multipliers

Unprotected

50 100 150 200 250 100 200 300 400 500 #transitions cycles Mastrovito 233 200 225 250 cycles Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 48/62

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SLIDE 143

Protected Multipliers

Unprotected

50 100 150 200 250 100 200 300 400 500 #transitions cycles Mastrovito 233 200 225 250 cycles

Protected Overhead: Area/time < 10 % References: PhD D. Pamula [13] Articles: [16], [15], [14]

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 48/62

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SLIDE 144

Protected ECC Accelerator

100 200 300 50 100 150 200 250 300 350 #transit. cycles DBL operation Mastrovito Unprotected Activity trace 0.00 0.02 0.04 0.06 0.08 current [mA] DBL operation Mastrovito Unprotected Current measures 100 200 300 #transit. DBL operation Mastrovito Protected Activity trace 0.00 0.04 0.08 0.12 0.16 current [mA] DBL operation Mastrovito Protected Current measures 100 200 300 #transit. ADD operation Mastrovito Protected Activity trace

Warning: old dedicated accelerator (similar behavior is expected for our new one)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 49/62

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SLIDE 145

Arithmetic Level Countermeasures

Redundant number system =

  • a way to improve the performance of some operations
  • a way to represent a value with different representations

k R1(k) [R1(k)]P R2(k) [R2(k)]P R3(k) [R3(k)]P R4(k) [R4(k)]P R5(k) [R5(k)]P R6(k) [R6(k)]P R7(k) [R7(k)]P . . . . . .

Important property: ∀i [Ri(k)]P = [k]P Proposed solution: use random redundant representations of k

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 50/62

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SLIDE 146

Double-Base Number System

Standard radix-2 representation: k =

t−1

  • i=0

ki2i = kt−1 kt−2 . . . k2 k1 k0

t explicit digits

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 51/62

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SLIDE 147

Double-Base Number System

Standard radix-2 representation: k =

t−1

  • i=0

ki2i = kt−1

2t−1

kt−2

2t−2

. . .

. . .

k2

22

k1

21

k0

20 t explicit digits implicit weights

Digits: ki ∈ {0, 1}, typical size: t ∈ {160, . . . , 600}

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 51/62

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SLIDE 148

Double-Base Number System

Standard radix-2 representation: k =

t−1

  • i=0

ki2i = kt−1

2t−1

kt−2

2t−2

. . .

. . .

k2

22

k1

21

k0

20 t explicit digits implicit weights

Digits: ki ∈ {0, 1}, typical size: t ∈ {160, . . . , 600} Double-Base Number System (DBNS): k =

n−1

  • j=0

kj2aj3bj =

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 51/62

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SLIDE 149

Double-Base Number System

Standard radix-2 representation: k =

t−1

  • i=0

ki2i = kt−1

2t−1

kt−2

2t−2

. . .

. . .

k2

22

k1

21

k0

20 t explicit digits implicit weights

Digits: ki ∈ {0, 1}, typical size: t ∈ {160, . . . , 600} Double-Base Number System (DBNS): k =

n−1

  • j=0

kj2aj3bj = kn−1 an−1 bn−1 . . . . . . . . . k1 a1 b1 k0 a0 b0 n (2, 3)−terms explicit “digits” explicit ranks aj, bj ∈ N, kj ∈ {1} or kj ∈ {−1, 1}, size n ≈ log t

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 51/62

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SLIDE 150

Double-Base Number System

Standard radix-2 representation: k =

t−1

  • i=0

ki2i = kt−1

2t−1

kt−2

2t−2

. . .

. . .

k2

22

k1

21

k0

20 t explicit digits implicit weights

Digits: ki ∈ {0, 1}, typical size: t ∈ {160, . . . , 600} Double-Base Number System (DBNS): k =

n−1

  • j=0

kj2aj3bj = kn−1 an−1 bn−1 . . . . . . . . . k1 a1 b1 k0 a0 b0 n (2, 3)−terms explicit “digits” explicit ranks aj, bj ∈ N, kj ∈ {1} or kj ∈ {−1, 1}, size n ≈ log t DBNS is a very redundant and sparse representation:

1701 = (11010100101)2

1701 = 243 + 1458 = 2035 + 2136 = (1, 0, 5), (1, 1, 6) = 1728 − 27 = 2633 − 2033 = (1, 6, 3), (−1, 0, 3) = 729 + 972 = 2036 + 2235 = (1, 0, 6), (1, 2, 5) . . .

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 51/62

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SLIDE 151

Randomized DBNS Recoding of the Scalar k

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P) TPL(P)

curve level

x±y x×y . . .

field level

On-the-fly DBNS random recoding for the scalar k randomly recode windows of the scalar k on-the-fly: 1 + 2 ⇆ 3 1 + 3 ⇆ 22 1 + 23 ⇆ 32 . . . control number of reductions (←) and expansions (→) Point tripling operation Q = TPL(P) = P + P + P k

ki block time

recoding rules possible rules

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 52/62

slide-152
SLIDE 152

Randomized DBNS Recoding of the Scalar k

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P) TPL(P)

curve level

x±y x×y . . .

field level

On-the-fly DBNS random recoding for the scalar k randomly recode windows of the scalar k on-the-fly: 1 + 2 ⇆ 3 1 + 3 ⇆ 22 1 + 23 ⇆ 32 . . . control number of reductions (←) and expansions (→) Point tripling operation Q = TPL(P) = P + P + P k

ki block time

recoding rules possible rules

recoded ki (,ki+1)

random choice

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 52/62

slide-153
SLIDE 153

Randomized DBNS Recoding of the Scalar k

encryption signature etc

protocol level

[k]P ADD(P, Q) DBL(P) TPL(P)

curve level

x±y x×y . . .

field level

On-the-fly DBNS random recoding for the scalar k randomly recode windows of the scalar k on-the-fly: 1 + 2 ⇆ 3 1 + 3 ⇆ 22 1 + 23 ⇆ 32 . . . control number of reductions (←) and expansions (→) Point tripling operation Q = TPL(P) = P + P + P k

ki block time

recoding rules possible rules

recoded ki (,ki+1)

random choice

DBNS is redundant ⇒ security ր DBNS is sparse ⇒ 20–30 % speed ր Ref: [7] Chabrier, Pamula & Tisserand. Asilomar 2009

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 52/62

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SLIDE 154

Hardware Implementation of RNS for ECC (1/2)

RNS: Residue Number System

  • Base B = (m1, m2, . . . , mk) of k relatively prime moduli
  • Size of the base: k

A = {a1, a2, . . . , ak}, ∀i ai = A mod mi Operations: A ± B = (|a1 ± b1|m1, . . . , |ak ± bk|mk) A × B = (|a1 × b1|m1, . . . , |ak × bk|mk)

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 53/62

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SLIDE 155

Hardware Implementation of RNS for ECC (2/2)

Rower 1 w w

mod3

Rower 2 w w

mod3

. . . . . .

Rower n w w

mod3

Cox

mod3

|q|3 |q|4 |s|4 |s|3 . . . . . .

. . .

t + 2

. . . registers I/O w

channel 1

w w 2

channel 2

w w 2

channel n

w w 2

. . . . . .

CTRL

30-state FSM

. . . . . .

CTRL (shared) local reg. {@, en, r/w}

Arithmetic Unit (6 pipeline stages)

{rst, mode, . . .}

w w w w w

IN

w

OUT

w

mod3 OUT mod3

2

cmp

w

= 1 = −1 precomp. mult. ≈ 2n × w

w

@1

precomp. ri (×2)

@2

⌈log2 ri⌉ precomp. add. 38 × w

@3

w

Optimized algorithms and implementations for GF(p) operations:

  • fast operations: inversion [3], modular multiplication [5], patterns [4]
  • PhD Thesis Karim Bigou [2]
  • hybrid positio-residues (HPR) representation [6]

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 54/62

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SLIDE 156

Comparison ECC 256 vs HECC 128 (1/2)

area [slices] time [ms]

ECC HECC

600 800 1000 1200 1400 1600 1800 2000 2200 5 10 15 20 25 30 5,4 5,2 5,1 4,4 4,2 4,1 3,4 3,2 3,1 2,4 2,2 2,1 1,4 1,2 1,1 12,2 12,1 11,2 11,1 10,2 10,1 9,2 9,1 8,2 8,1 7,2 7,1 6,2 6,1 5,2 5,1 4,2 4,1 3,2 3,1 2,2 2,1 1,2 1,1

On average HECC is 40 % faster than ECC for a similar silicon cost

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 55/62

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SLIDE 157

Comparison ECC 256 vs HECC 128 (2/2)

% usage × area speedup

ECC HECC

20 40 60 80 100 1 2 3 1 2 3 4 5 1,1 1,2 1,4 2,4 3,4 4,4 1,1 1,2 2,1 3,1 3,2 5,2 8,2

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 56/62

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SLIDE 158

Conclusion

  • Side channel and fault attacks are serious threats
  • Attacks are more and more efficient (many variants)
  • Security analysis is mandatory at all levels (specification, algorithm,
  • peration, implementation)
  • Security = trade-off between performances, robustness and cost
  • Security = func( secret value, attacker capabilities )
  • security = computer science + microelectronics + mathematics

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 57/62

slide-159
SLIDE 159

Conclusion

  • Side channel and fault attacks are serious threats
  • Attacks are more and more efficient (many variants)
  • Security analysis is mandatory at all levels (specification, algorithm,
  • peration, implementation)
  • Security = trade-off between performances, robustness and cost
  • Security = func( secret value, attacker capabilities )
  • security = computer science + microelectronics + mathematics

Current works examples:

  • Methods/tools for automating security analysis
  • Circuit reconfiguration (representations, algorithms)
  • Circuits with reduced activity variations
  • Representation of numbers with error detection/correction “codes”
  • Design space exploration
  • CAD tools with security improvement capabilities

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 57/62

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SLIDE 160

Our Long Term Objectives

Study the links between:

  • cryptosystems
  • arithmetic algorithms
  • Fq, pts representations
  • architectures & units
  • circuit optimisations

to ensure

  • high security against

◮ theoretical attacks ◮ physical attacks

  • low design cost
  • low silicon cost
  • low energy(/power)
  • high performances
  • high flexibility

area 1 delay 1 energy 1 security 1

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 58/62

slide-161
SLIDE 161

Our Long Term Objectives

Study the links between:

  • cryptosystems
  • arithmetic algorithms
  • Fq, pts representations
  • architectures & units
  • circuit optimisations

to ensure

  • high security against

◮ theoretical attacks ◮ physical attacks

  • low design cost
  • low silicon cost
  • low energy(/power)
  • high performances
  • high flexibility

area 1 1 + a delay 1 1 + t energy 1 1 + e a, t, e ∈ 0%, 5%, 10%, . . . , 100% security 1

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 58/62

slide-162
SLIDE 162

Our Long Term Objectives

Study the links between:

  • cryptosystems
  • arithmetic algorithms
  • Fq, pts representations
  • architectures & units
  • circuit optimisations

to ensure

  • high security against

◮ theoretical attacks ◮ physical attacks

  • low design cost
  • low silicon cost
  • low energy(/power)
  • high performances
  • high flexibility

area 1 1 + a delay 1 1 + t energy 1 1 + e a, t, e ∈ 0%, 5%, 10%, . . . , 100% security 1 ×10 ×100

Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 58/62

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SLIDE 163

References I

[1]

  • J. Balasch, B. Gierlichs, and I. Verbauwhede.

An in-depth and black-box characterization of the effects of clock glitches on 8-bit MCUs. In Proc. 8th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pages 105–114, Nara, Japan, September 2011. IEEE. [2]

  • K. Bigou.

´ Etude th´ eorique et implantation mat´ erielle d’unit´ es de calcul en repr´ esentation modulaire des nombres pour la cryptographie sur courbes elliptiques. Phd thesis, University Rennes 1, Lannion, France, November 2014. [3]

  • K. Bigou and A. Tisserand.

Improving modular inversion in RNS using the plus-minus method. In G. Bertoni and J.-S. Coron, editors, Proc. 15th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), volume 8086 of LNCS, pages 233–249, Santa Barbara, CA, USA, August 2013. Springer. [4]

  • K. Bigou and A. Tisserand.

RNS modular multiplication through reduced base extensions. In H. Fu and D. Thomas, editors, Proc. 25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pages 57–62, Zurich, Switzerland, June 2014. IEEE. [5]

  • K. Bigou and A. Tisserand.

Single base modular multiplication for efficient hardware RNS implementations of ECC. In T. Guneysu and H. Handschuh, editors, Proc. 17th International Workshop on Cryptographic Hardware and Embedded Systems (CHES), volume 9293 of LNCS, pages 123–140, Saint-Malo, France, September 2015. Springer. [6]

  • K. Bigou and A. Tisserand.

Hybrid position-residues number system. In J. Hormigo, S. Oberman, and N. Revol, editors, Proc. 23rd Symposium on Computer Arithmetic (ARITH), pages 126–133, Santa Clara, CA, U.S.A, July 2016. IEEE Computer Society. [7]

  • T. Chabrier, D. Pamula, and A. Tisserand.

Hardware implementation of DBNS recoding for ECC processor. In Proc. 44rd Asilomar Conference on Signals, Systems and Computers, pages 1129–1133, Pacific Grove, California, U.S.A., November 2010. IEEE. Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 59/62

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SLIDE 164

References II

[8]

  • J. Chen, A. Tisserand, E. M. Popovici, and S. Cotofana.

Robust sub-powered asynchronous logic. In J. Becker and M. R. Adrover, editors, Proc. 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 1–7, Palma de Mallorca, Spain, September 2014. IEEE. [9]

  • J. Chen, A. Tisserand, E. M. Popovici, and S. Cotofana.

Asynchronous charge sharing power consistent Montgomery multiplier. In J. Sparso and E Yahya, editors, Proc. 21st IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC), pages 132–138, Mountain View, California, USA, May 2015. [10]

  • S. Endo, T. Sugawara, N. Homma, T. Aoki, and A. Satoh.

An on-chip glitchy-clock generator for testing fault injection attacks. Journal of Cryptographic Engineering, 1(4):265–270, December 2011. [11]

  • P. C. Kocher, J. Jaffe, and B. Jun.

Differential power analysis. In Proc. Advances in Cryptology (CRYPTO), volume 1666 of LNCS, pages 388–397. Springer, August 1999. [12]

  • N. Moro, A. Dehbaoui, K. Heydemann, B. Robisson, and E. Encrenaz.

Electromagnetic fault injection: Towards a fault model on a 32-bit microcontroller. In Proc. 10th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pages 77–88, Santa Barbara, CA, USA, August 2013. IEEE. [13]

  • D. Pamula.

Arithmetic Operators on GF(2m) for Cryptographic Applications: Performance - Power Consumption - Security Tradeoffs. Phd thesis, University of Rennes 1 and Silesian University of Technology, December 2012. [14]

  • D. Pamula, E. Hrynkiewicz, and A. Tisserand.

Analysis of GF(2233) multipliers regarding elliptic curve cryptosystem applications. In 11th IFAC/IEEE International Conference on Programmable Devices and Embedded Systems (PDeS), pages 271–276, Brno, Czech Republic, May 2012. Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 60/62

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SLIDE 165

References III

[15]

  • D. Pamula and A. Tisserand.

GF(2m) finite-field multipliers with reduced activity variations. In 4th International Workshop on the Arithmetic of Finite Fields, volume 7369 of LNCS, pages 152–167, Bochum, Germany, July 2012. Springer. [16]

  • D. Pamula and A. Tisserand.

Fast and secure finite field multipliers. In Proc. 18th Euromicro Conference on Digital System Design (DSD), pages 653–660, Madeira, Portugal, August 2015. [17]

  • R. L. Rivest, A. Shamir, and L. Adleman.

A method for obtaining digital signatures and public-key cryptosystems. Communications of the ACM, 21(2):120–126, February 1978. [18]

  • J. Schmidt and C. Herbst.

A practical fault attack on square and multiply. In Proc. 5th International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pages 53–58, Washington, DC, USA, August 2008. IEEE. [19]

  • N. Selmane, S. Guilley, and J.-L. Danger.

Practical setup time violation attacks on AES. In Proc. 7th European Dependable Computing Conference (EDCC), Kaunas, Lithuania, 2008. Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 61/62

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SLIDE 166

The end, questions ?

Contact:

  • mailto:arnaud.tisserand@univ-ubs.fr
  • http://www-labsticc.univ-ubs.fr/~tisseran
  • CNRS, Lab-STICC Laboratory

University South Brittany (UBS), Centre de recherche C. Huygens, rue St Maud´ e, BP 92116, 56321 Lorient cedex, France Thank you

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