RSA Asymmetric Cryptosystem (2/2) Private key (Alice): d Public key (all): ( n , e ) Encryption (Bob side): • convert the message M to an integer m (1 < m < n and gcd( m , n ) = 1) • compute the cipher text c = m e mod n Decryption (Alice side): • compute m = c d mod n • convert the integer m to the message M Theoretical security : integer factorization, i.e. computing ( p , q ) knowing n , is not possible when n is large enough Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 10/62
Modular Exponentiation Computation of operations such as : a b mod n a b = a × a × a × a × . . . × a × a × a � �� � a appears b times Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 11/62
Modular Exponentiation Computation of operations such as : a b mod n a b = a × a × a × a × . . . × a × a × a � �� � a appears b times Order of magnitude of exponents: 2 size of exponent � 2 1024 . . . 2 2048 . . . 2 4096 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 11/62
Modular Exponentiation Computation of operations such as : a b mod n a b = a × a × a × a × . . . × a × a × a � �� � a appears b times Order of magnitude of exponents: 2 size of exponent � 2 1024 . . . 2 2048 . . . 2 4096 Fast exponentiation principle: a b = b ( a 2 ) when b is even 2 b − 1 a × ( a 2 ) = when b is odd 2 Least significant bit of the exponent: bit = 0 � even and bit = 1 � odd Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 11/62
Square and Multiply Algorithm input : a , b , n where b = ( b t − 1 b t − 2 . . . b 1 b 0 ) 2 output : a b mod n r = 1 for i from 0 to t − 1 do b i = 1 then i f r = r · a mod n endif a = a 2 mod n endfor return r This is the right to left version (there exists a left to right one) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 12/62
Hardware Accelerators for Elliptic Curve Crypto. protocol level encryption signature etc [ k ] P curve level P + P ADD ( P , Q ) DBL ( P ) field level x ± y x × y . . . Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62
Hardware Accelerators for Elliptic Curve Crypto. E : y 2 = x 3 + 4 x + 20 over GF(1009) protocol level points: P , Q = ( x , y ) or ( x , y , z ) or . . . encryption signature etc [ k ] P curve level P + P ADD ( P , Q ) DBL ( P ) field level x ± y x × y . . . Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62
Hardware Accelerators for Elliptic Curve Crypto. E : y 2 = x 3 + 4 x + 20 over GF(1009) protocol level points: P , Q = ( x , y ) or ( x , y , z ) or . . . encryption signature coordinates: x , y , z ∈ GF ( · ) etc GF ( p ), GF (2 m ), t : 200–600 bits k = ( k t − 1 k t − 2 . . . k 1 k 0 ) 2 ∈ N [ k ] P curve level P + P ADD ( P , Q ) DBL ( P ) field level x ± y x × y . . . Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62
Hardware Accelerators for Elliptic Curve Crypto. E : y 2 = x 3 + 4 x + 20 over GF(1009) protocol level points: P , Q = ( x , y ) or ( x , y , z ) or . . . encryption signature coordinates: x , y , z ∈ GF ( · ) etc GF ( p ), GF (2 m ), t : 200–600 bits k = ( k t − 1 k t − 2 . . . k 1 k 0 ) 2 ∈ N Scalar multiplication operation [ k ] P for i from 0 to t − 1 do curve level if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) P + P ADD ( P , Q ) DBL ( P ) field level x ± y x × y . . . Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62
Hardware Accelerators for Elliptic Curve Crypto. E : y 2 = x 3 + 4 x + 20 over GF(1009) protocol level points: P , Q = ( x , y ) or ( x , y , z ) or . . . encryption signature coordinates: x , y , z ∈ GF ( · ) etc GF ( p ), GF (2 m ), t : 200–600 bits k = ( k t − 1 k t − 2 . . . k 1 k 0 ) 2 ∈ N Scalar multiplication operation [ k ] P for i from 0 to t − 1 do curve level if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) P + P Point addition/doubling operations ADD ( P , Q ) DBL ( P ) sequence of finite field operations DBL : v 1 = z 2 1 , v 2 = x 1 − v 1 , . . . ADD : w 1 = z 2 1 , w 2 = z 1 × w 1 , . . . field level x ± y x × y . . . Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62
Hardware Accelerators for Elliptic Curve Crypto. E : y 2 = x 3 + 4 x + 20 over GF(1009) protocol level points: P , Q = ( x , y ) or ( x , y , z ) or . . . encryption signature coordinates: x , y , z ∈ GF ( · ) etc GF ( p ), GF (2 m ), t : 200–600 bits k = ( k t − 1 k t − 2 . . . k 1 k 0 ) 2 ∈ N Scalar multiplication operation [ k ] P for i from 0 to t − 1 do curve level if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) P + P Point addition/doubling operations ADD ( P , Q ) DBL ( P ) sequence of finite field operations DBL : v 1 = z 2 1 , v 2 = x 1 − v 1 , . . . ADD : w 1 = z 2 1 , w 2 = z 1 × w 1 , . . . field level GF ( p ) or GF (2 m ) operations x ± y x × y . . . operation modulo large prime ( GF ( p )) or irreducible polynomial ( GF (2 m )) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 13/62
Attacks attack Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62
Attacks observation attack perturbation invasive Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62
Attacks timing analysis power analysis EMR analysis observation attack perturbation fault injection invasive reverse engineering probing EMR = Electromagnetic radiation Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62
Attacks timing analysis power analysis EMR analysis observation attack perturbation theoretical fault injection invasive reverse engineering probing EMR = Electromagnetic radiation Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62
Attacks timing analysis power analysis EMR analysis observation attack perturbation theoretical fault injection invasive reverse engineering advanced algorithms probing optimized programming EMR = Electromagnetic radiation Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 14/62
Side Channel Attacks (SCAs) (1/2) Attack : attempt to find, without any knowledge about the secret: • the message (or parts of the message) • informations on the message • the secret (or parts of the secret) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 15/62
Side Channel Attacks (SCAs) (1/2) Attack : attempt to find, without any knowledge about the secret: • the message (or parts of the message) • informations on the message • the secret (or parts of the secret) “Old style” side channel attacks : + good value clic clac bad value Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 15/62
Side Channel Attacks (SCAs) (2/2) E D E k ( M ) D k ( E k ( M )) = M M A B k k General principle: measure external parameter(s) on running device in order to deduce internal informations Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 16/62
Side Channel Attacks (SCAs) (2/2) E D E k ( M ) D k ( E k ( M )) = M M A B k k measure attack k , M ??? E General principle: measure external parameter(s) on running device in order to deduce internal informations Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 16/62
What Should be Measured? Answer : everything that can “enter” and/or “get out” in/from the device • power consumption • electromagnetic radiation • temperature • sound • computation time • number of cache misses • number and type of error messages • ... The measured parameters may provide informations on: • global behavior (temperature, power, sound...) • local behavior (EMR, # cache misses...) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 17/62
Power Consumption Analysis General principle: 1. measure the current i ( t ) in the cryptosystem 2. use those measurements to “deduce” secret informations crypto. secret key = 962571. . . i ( t ) R V DD traces Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 18/62
Simple Power Analysis (SPA) Source: [11] Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 19/62
Simple Power Analysis (SPA) Source: [11] Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 19/62
Limits of the SPA Example of behavior difference: (activity into a register) t 0000000000000000 0000000000000000 t + 1 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62
Limits of the SPA Example of behavior difference: (activity into a register) t 0000000000000000 0000000000000000 t + 1 1111111111111111 0000000000000001 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62
Limits of the SPA Example of behavior difference: (activity into a register) t 0000000000000000 0000000000000000 t + 1 1111111111111111 0000000000000001 Important : a small difference may be evaluated has a noise during the measurement traces cannot be distinguished Question : what can be done when differences are too small? Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62
Limits of the SPA Example of behavior difference: (activity into a register) t 0000000000000000 0000000000000000 t + 1 1111111111111111 0000000000000001 Important : a small difference may be evaluated has a noise during the measurement traces cannot be distinguished Question : what can be done when differences are too small? Answer : use statistics over several traces Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 20/62
Differential Power Analysis (DPA) cryptosystem Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem internal state Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem internal state select bit b to attack b = 1 b = 0 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem implementation internal state select bit b to attack b = 1 b = 0 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem implementation internal state power model select bit b to attack b = 1 b = 0 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem implementation internal state power model select bit b to attack power( H b =1 ) b = 1 power( H b =0 ) b = 0 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem implementation internal state measures power model select bit b to attack power( H b =1 ) b = 1 power( H b =0 ) b = 0 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Differential Power Analysis (DPA) cryptosystem implementation internal state measures power model select bit b to attack power( H b =1 ) b = 1 comparison power( H b =0 ) b = 0 correct hypothesis Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 21/62
Template Attack cryptosystem Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Template Attack cryptosystem internal state Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Template Attack cryptosystem internal state select variable v to attack v = 0 v = 1 v = 2 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Template Attack cryptosystem implementation internal state select variable v to attack v = 0 v = 1 v = 2 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Template Attack cryptosystem implementation internal state measures select variable v to attack v = 0 power( v = 0) power( v = 1) v = 1 power( v = 2) v = 2 training step Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Template Attack cryptosystem implementation internal state measures measures select variable v to attack v = 0 power( v = 0) power( v = 1) v = 1 power( v = 2) v = 2 training step Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Template Attack cryptosystem implementation internal state measures measures select variable v to attack v = 0 power( v = 0) power( v = 1) comparison v = 1 power( v = 2) v = 2 training step correct hypothesis Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 22/62
Electromagnetic Radiation Analysis General principle : use a probe to measure the EMR V DD circuit GND EMR measurement : Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 23/62
Electromagnetic Radiation Analysis General principle : use a probe to measure the EMR V DD circuit GND EMR measurement : • global EMR with a large probe Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 23/62
Electromagnetic Radiation Analysis General principle : use a probe to measure the EMR V DD circuit GND EMR measurement : • global EMR with a large probe • local EMR with a micro-probe Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 23/62
Side Channel Attack on ECC protocol level encryption signature etc [ k ] P curve level Scalar multiplication operation ADD ( P , Q ) DBL ( P ) for i from 0 to t − 1 do if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) field level . . . x ± y x × y Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 24/62
Side Channel Attack on ECC protocol level encryption signature etc [ k ] P curve level Scalar multiplication operation ADD ( P , Q ) DBL ( P ) for i from 0 to t − 1 do if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) field level . . . x ± y x × y Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 24/62
Side Channel Attack on ECC protocol level DBL DBL DBL DBL DBL DBL encryption signature etc [ k ] P curve level Scalar multiplication operation ADD ( P , Q ) DBL ( P ) for i from 0 to t − 1 do if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) field level . . . x ± y x × y Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 24/62
Side Channel Attack on ECC protocol level DBL DBL DBL ADD DBL ADD DBL DBL encryption signature etc [ k ] P curve level Scalar multiplication operation ADD ( P , Q ) DBL ( P ) for i from 0 to t − 1 do if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) field level . . . x ± y x × y Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 24/62
Side Channel Attack on ECC protocol level DBL DBL DBL ADD DBL ADD DBL DBL encryption signature etc 0 0 0 1 1 0 [ k ] P curve level Scalar multiplication operation ADD ( P , Q ) DBL ( P ) for i from 0 to t − 1 do if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) • simple power analysis (& variants) field level . . . x ± y x × y Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 24/62
Side Channel Attack on ECC protocol level DBL DBL DBL ADD DBL ADD DBL DBL encryption signature etc 0 0 0 1 1 0 [ k ] P curve level Scalar multiplication operation ADD ( P , Q ) DBL ( P ) for i from 0 to t − 1 do if k i = 1 then Q = ADD ( P , Q ) P = DBL ( P ) • simple power analysis (& variants) field level . . . x ± y x × y • differential power analysis (& variants) • horizontal/vertical/templates/. . . attacks Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 24/62
Fault Injection Attacks Objective : alter the correct functioning of a system “from outside” Fault effects examples : • modify a value in a register • modify a value in the memory hierarchy • modify an address (data location or code location) • modify a control signal (e.g. status flag, branch direction) • skip/modify the instruction decoding • delay/advance propagation of internal control signals • etc. Also called perturbation attacks Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 25/62
Fault Injection Techniques Typical techniques : • perturbation in the power supply voltage • perturbation of the clock signal • temperature (over/under-heating the chip) • radiation or electromagnetic (EM) disturbances • exposing the chip to intense lights or beams • etc Accuracy : • time: part of clock cycle, clock cycle, code block (instruction sequence) • space: gate, block, unit, core, chip, package • value: set to a specific value, bit flip, stuck-at 0 or 1, random modification Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 26/62
Perturbation on the Power Supply Principle : controlled power supply voltage time • Nominal power supply (e.g. ≈ [0 . 7 , 1 . 2] V for current technologies) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 27/62
Perturbation on the Power Supply Principle : V DD controlled device power under supply attack GND voltage time • Nominal power supply (e.g. ≈ [0 . 7 , 1 . 2] V for current technologies) • Non-nominal constant power supply (e.g. 0 . 7 V instead of 1 . 2 V) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 27/62
Perturbation on the Power Supply Principle : V DD power controlled device device glitch power under under generator supply attack attack GND voltage time • Nominal power supply (e.g. ≈ [0 . 7 , 1 . 2] V for current technologies) • Non-nominal constant power supply (e.g. 0 . 7 V instead of 1 . 2 V) • Glitches (dips, spikes) in the power supply at some selected moments Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 27/62
Under Powering Example Source : paper [19] presented at EDCC 2008 conference Setup : 130 nm smart card (1.2 V nominal V DD ) with AES crypto-processor Measurement campaign : triples (msg, key, cypher) recorded for 100 V DD in [775, 825] mV over 20,000 encryptions with comparison to a (RTL) simulation for one byte corruption in the state matrix at various rounds Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 28/62
Under Powering Example Source : paper [19] presented at EDCC 2008 conference Setup : 130 nm smart card (1.2 V nominal V DD ) with AES crypto-processor Measurement campaign : triples (msg, key, cypher) recorded for 100 V DD in [775, 825] mV over 20,000 encryptions with comparison to a (RTL) simulation for one byte corruption in the state matrix at various rounds Observed behavior is compatible with setup violation model on a critical path (bell shape due to only one or multiple paths) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 28/62
Under Powering Example Source : paper [19] presented at EDCC 2008 conference Setup : 130 nm smart card (1.2 V nominal V DD ) with AES crypto-processor Measurement campaign : triples (msg, key, cypher) recorded for 100 V DD in [775, 825] mV over 20,000 encryptions with comparison to a (RTL) simulation for one byte corruption in the state matrix at various rounds Observed behavior is compatible with setup violation model on a critical path (bell shape due to only one or multiple paths) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 28/62
Power Glitching Example Source : FDTC 2008 conference paper [18] Setup : AVR microcontroller with RSA implementation Attack result : a power glitch causes to skip some instruction Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 29/62
Perturbation on the External Clock Principle : voltage CLK time • Normal clock (at a given frequency, duty cycle ≈ 50%) Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 30/62
Perturbation on the External Clock Principle : voltage MCLK CLK time • Normal clock (at a given frequency, duty cycle ≈ 50%) • Clock with a modified duty cycle Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 30/62
Perturbation on the External Clock Principle : voltage glitches GCLK MCLK CLK time • Normal clock (at a given frequency, duty cycle ≈ 50%) • Clock with a modified duty cycle • Glitched clock • Etc. Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 30/62
Glitchy Clock Generation Example Source : paper [10] published in J. Crypto. Eng. 2011 Setup : Virtex-II Pro FPGA (on SASEBO card) used to generate a “glitchy” clock for several programmable time parameters Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 31/62
Clock Glitch Attack Example Source : paper [1] presented at FDTC 2011 conference Setup : AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction opcode (bin) normal - 0000 0000 0000 0000 i NOP normal - i + 1 EOR R15,R5 0010 0100 1111 0101 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 32/62
Clock Glitch Attack Example Source : paper [1] presented at FDTC 2011 conference Setup : AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction opcode (bin) normal - 0000 0000 0000 0000 i NOP normal - i + 1 EOR R15,R5 0010 0100 1111 0101 glitch 59 ns i + 1 NOP 0000 0000 0000 0000 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 32/62
Clock Glitch Attack Example Source : paper [1] presented at FDTC 2011 conference Setup : AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction opcode (bin) normal - 0000 0000 0000 0000 i NOP normal - i + 1 EOR R15,R5 0010 0100 1111 0101 glitch 59 ns i + 1 NOP 0000 0000 0000 0000 mode glitch period cycle instruction opcode (bin) normal - 0000 0000 0000 0000 i NOP normal - i + 1 SER R18 1110 1111 0010 1111 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 32/62
Clock Glitch Attack Example Source : paper [1] presented at FDTC 2011 conference Setup : AVR ATMega 163 microcontroller @ 1MHz mode glitch period cycle instruction opcode (bin) normal - 0000 0000 0000 0000 i NOP normal - i + 1 EOR R15,R5 0010 0100 1111 0101 glitch 59 ns i + 1 NOP 0000 0000 0000 0000 mode glitch period cycle instruction opcode (bin) normal - 0000 0000 0000 0000 i NOP normal - i + 1 SER R18 1110 1111 0010 1111 glitch 61 ns i + 1 LDI R18,0xEF 1110 1110 0010 1111 glitch 60 ns i + 1 0000 1000 0010 1111 SBC R12,R15 glitch 59 ns i + 1 NOP 0000 0000 0000 0000 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 32/62
mode glitch period cycle instruction opcode (bin) normal - 0010 0000 1100 1100 i TST R12 normal - i + 1 BREQ PC+0x02 1111 0000 0000 1001 normal - i + 2 1110 1111 1010 1111 SER R26 Arnaud Tisserand. CNRS – Lab-STICC. Embedding Crypto in SoCs: Threats and Protections 33/62
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