Elliptic Curve Cryptography Erich Wenger and Mario Werner IAIK Graz - - PowerPoint PPT Presentation

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Elliptic Curve Cryptography Erich Wenger and Mario Werner IAIK Graz - - PowerPoint PPT Presentation

Nov 12, 2022 247 likes •473 views

Institute for Applied Information Processing and Communications (IAIK) Evaluating 16-bit Processors for Elliptic Curve Cryptography Erich Wenger and Mario Werner IAIK Graz University of Technology Erich.Wenger@iaik.tugraz.at

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http://www.iaik.tugraz.at

Institute for Applied Information Processing and Communications (IAIK) 1

TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Erich Wenger and Mario Werner

IAIK – Graz University of Technology Erich.Wenger@iaik.tugraz.at www.iaik.tugraz.at

Evaluating 16-bit Processors for Elliptic Curve Cryptography

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http://www.iaik.tugraz.at

Institute for Applied Information Processing and Communications (IAIK) 2

TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Overview

  • Motivation
  • Algorithms
  • Processors
  • Results
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http://www.iaik.tugraz.at

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Motivation

We want to:

  • Investigate current CPUs for ECC
  • Find their limitations
  • Save energy
  • Improve performance
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Institute for Applied Information Processing and Communications (IAIK) 4

TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Point Multiplication Algorithm

  • Montgomery Ladder [Hutter]
  • 7 registers
  • Point Verification [Ebeid]
  • Randomized Projective Coordinates [Coron]
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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Multi-Precision Multiplication

  • Operand Scanning
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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

MSP430

  • Manufacturer: Texas Instruments
  • Low-Power RISC Processor
  • 16 Registers (12 useable)
  • 27 Instructions
  • Memory Mapped

Multiplier

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Institute for Applied Information Processing and Communications (IAIK) 7

TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

MSP430 – Operand Scanning

  • uter_loop:

MOV.W @R12+, &MPY inner_loop: MOV.W @R13+, &OP2 ADD.W &RESLO, R6 ADDC.W &RESHI, R7

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Institute for Applied Information Processing and Communications (IAIK) 8

TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

MSP430 – Product Scanning

inner_loop: MOV.W @R12+, &MAC MOV.W @R13 , &OP2 DECD R13 ADD.W &SUMEXT, R11

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Institute for Applied Information Processing and Communications (IAIK) 9

TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

PIC24 vs. dsPIC

Both Processors:

  • 16-bit RISC
  • 24-bit Instruction

Word

  • 16 registers (14

useable)

  • Used for:
  • Motor Control
  • Signal Processing

dsPIC:

  • Digital Signal

Processing Engine

  • Multiply-Accumulate
  • Two Address

Generation Units

  • Loop Instructions
  • DO
  • REPEAT
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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

dsPIC – Product Scanning

  • 16-bit Multiplication
  • 32-bit Addition (plus Overflow)

𝐵𝐷𝐷 ← 𝐵𝐷𝐷 + 𝐵 𝑗 ∙ 𝐶 𝑘

  • Load A[i] and B[j]
  • Memory Addressing (𝑗 ← 𝑗 + 1 , 𝑘 ← 𝑘 − 1)

REPEAT W4 MAC W5*W6, A, [W8]+=2, W5, [W10]-=2, W6

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

dsPIC – Unrolled Product Scanning

MAC W5*W6, A, [W9]-=2, W5, [W11]+=2, W6 MAC W5*W6, A, [W9], W5, [W11]+=2, W6 MAC W5*W6, A, [W9]+=2, W5, [W11]-=2, W6 MOV [W7],[W2++] SFTAC A, #16 MAC W5*W6, A, [W9]+=2, W5, [W11]-=2, W6 MAC W5*W6, A, [W9]+=2, W5, [W11]-=2, W6 MAC W5*W6, A, [W9]+=2, W5, [W11], W6 MAC W5*W6, A, [W9]-=2, W5, [W11]+=2, W6 MOV [W7],[W2++] SFTAC A, #16

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

dsPIC – Montgomery Multiplication

𝑆 = 2𝑋𝑂 > 𝑞 ෤ 𝑏 ≡ 𝑏𝑆 (𝑛𝑝𝑒 𝑞) ෨ 𝑐 ≡ 𝑐𝑆 𝑛𝑝𝑒 𝑞 ǁ 𝑑 ≡ 𝑁𝑝𝑜𝑢 ෤ 𝑏෨ 𝑐 ≡ 𝑏𝑆 𝑐𝑆 𝑆−1 ≡ 𝑏𝑐𝑆 ≡ 𝑑𝑆 𝑛𝑝𝑒 𝑞 ෤ 𝑏 ≡ 𝑁𝑝𝑜𝑢 𝑏, 𝑆2 ≡ 𝑏𝑆2𝑆−1 ≡ 𝑏𝑆 𝑑 ≡ 𝑁𝑝𝑜𝑢( ǁ 𝑑, 1) ≡ (𝑑𝑆)𝑆−1 NIST Reduction…

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Results

  • SECG:
  • secp160r1

removed in 2010

  • NIST:
  • P-192
  • P-224
  • P-256
  • IAR Embedded Workbench 5.20
  • Microchip MPLAB C30 v3.25
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Results: MSP430

0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50

Speedup

Multiplication Field Multiplication Point Multiplication

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Results: PIC24, dsPIC

1 2 3 4 5 6 7 8 9 10 Speedup Multiplication Field Multiplication Point Multiplication

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Results: Point Multiplication

0,5 1 1,5 2 2,5 3 3,5

  • p. sc.

hybrid

  • p. sc.
  • p. sc.
  • pr. sc.

Mont. C ASM C ASM ASM + DSP ASM + DSP MSP430 MSP430 PIC24 PIC24 dsPIC dsPIC Speedup secp160r1 P-192 P-224 P-256

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Results: Point Multiplication

5 10 15

  • p. sc.

hybrid

  • p. sc.
  • p. sc.
  • pr. sc.

Mont. C ASM C ASM ASM + DSP ASM + DSP MSP430 MSP430 PIC24 PIC24 dsPIC dsPIC Speedup secp160r1 P-192 P-224 P-256

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Results: Point Multiplication

1 2 3 4 5 6

  • p. sc.

hybrid

  • p. sc.
  • p. sc.
  • pr. sc.

Mont. C ASM C ASM ASM + DSP ASM + DSP MSP430 MSP430 PIC24 PIC24 dsPIC dsPIC Speedup secp160r1 P-192 P-224 P-256

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Results: Related Work

500 1000 1500 2000 2500 3000 ASM + DSP Yan 2009 Kern 2010 Wenger 2010 Hutter 2010 dsPIC C6416 ASIC ASIC ASIC Runtime [kCycles] secp160r1 P-192 P-224

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Thank you…

This work has been supported by the Austrian Government through the research program FIT-IT Trust in IT Systems under the project number 825743 (project PIT).

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TU Graz/Computer Science/IAIK/SEnSE/Erich Wenger CARDIS

Results

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Results