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September 23rd, 2004 IWSBP2004 2
Content
Basic ideas Definition of the architecture Summary and outlook
Efficient Reprogrammable Architecture for Boolean Functions and - - PowerPoint PPT Presentation
Efficient Reprogrammable Architecture for Boolean Functions and - - PowerPoint PPT Presentation
Harald Richter, Christian Siemers: Efficient Reprogrammable Architecture for Boolean Functions and Cellular Automata Content Basic ideas Definition of the architecture Summary and outlook September 23rd, 2004 IWSBP2004 2 Basic
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September 23rd, 2004 IWSBP2004 3
Basic Ideas (1)
Two sources for this approach:
Looking for a general computing model
to be used inside programmable logic devices
Looking for a memory-based
programmable logic device architecture
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September 23rd, 2004 IWSBP2004 4
Basic Ideas (2)
General computing model:
Global cellular automata are a very
good candidate
Cellular automaton:
Finite set of finite state machines (FSM)
arranged in a k-dimensonal array
Communication is defined to nearest
neighbours (e.g. 4). Each FSM can read but not write.
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Basic Ideas (3)
General computing model:
Global cellular automaton (GCA):
Communication is defined to all
members of the CA.
Avoiding communication time penalties
inside CA.
CA and GCA are known as general
purpose computer architecture
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September 23rd, 2004 IWSBP2004 6
Basic Ideas (4)
Implementing a GCA inside
programmable logic devices
Using N FSMs results in O(N²)
communication effort
The number of states per FSM is not
limited
No commercially available device (or
achitecture) is well-suited for implementing GCAs
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September 23rd, 2004 IWSBP2004 7
Basic Ideas (5)
New approach:
Omitting communication overhead by
putting all FSM into one logic block
Dividing the logic block into at least two
subblocks for efficient implemenation
Using memory arrays (look-up tables)
for each of the subblocks
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Definition of the Architecture (1)
RAM 256*8 RAM 256*8 RAM 256*8 RAM 256*8 RAM 256*8 RAM 256*8 RAM 256*8 RAM 256*8
8 8 8 8 8 8 8 8
Crossbar- Switch
64
RAM 64K*8 RAM 256*64
8
64 * >1 64 * =1 64 * 1 RAM 64K*8 RAM 256*64
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64 * >1 RAM 64K*8 RAM 256*64
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64 * >1 RAM 64K*8 RAM 256*64
8
64 * >1 RAM 64K*8 RAM 256*64
8
64 * D-Flipflop RAM 64K*8 RAM 256*64
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RAM 64K*8 RAM 256*64
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RAM 64K*8 RAM 256*64
8
64 * >1 64 * >1 64 * >1 Crossbar- Switch
8 8 8 8 8 8 8 8 64 16 16 16 16 16 16 16 16
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Definition of the Architecture (2)
The most important step is
to map the functionality on a CAM/RAM-structure
The example shows the
mapping of 216 locations with 12 bit each on the CAM/RAM network using 8 locations each
input CAM 8 lo- c ati-
- ns of
16 bits eac h i1
i nput stage
- utp ut stage
i16 i2 . . .
- 1
- 1 2
- 2
. . .
- ut-
put RAM 8 lo- cati-
- ns of
12 bits each a
1
a 2 a 3
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Summary and Outlook (1)
This architecture is very suited for
implementation in memory arrays
It comprises very good efficiency in
terms of space and energy consumption but low speed
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Summary and Outlook (2)
Open questions: