Harald Richter, Christian Siemers: Efficient Reprogrammable Architecture for Boolean Functions and Cellular Automata
Content � Basic ideas � Definition of the architecture � Summary and outlook September 23rd, 2004 IWSBP2004 2
Basic Ideas (1) � Two sources for this approach: � Looking for a general computing model to be used inside programmable logic devices � Looking for a memory-based programmable logic device architecture September 23rd, 2004 IWSBP2004 3
Basic Ideas (2) � General computing model: � Global cellular automata are a very good candidate � Cellular automaton: � Finite set of finite state machines (FSM) arranged in a k-dimensonal array � Communication is defined to nearest neighbours (e.g. 4). Each FSM can read but not write. September 23rd, 2004 IWSBP2004 4
Basic Ideas (3) � General computing model: � Global cellular automaton (GCA): � Communication is defined to all members of the CA. � Avoiding communication time penalties inside CA. � CA and GCA are known as general purpose computer architecture September 23rd, 2004 IWSBP2004 5
Basic Ideas (4) � Implementing a GCA inside programmable logic devices � Using N FSMs results in O( N ²) communication effort � The number of states per FSM is not limited � No commercially available device (or achitecture) is well-suited for implementing GCAs September 23rd, 2004 IWSBP2004 6
Basic Ideas (5) � New approach: � Omitting communication overhead by putting all FSM into one logic block � Dividing the logic block into at least two subblocks for efficient implemenation � Using memory arrays (look-up tables) for each of the subblocks September 23rd, 2004 IWSBP2004 7
Definition of the Architecture (1) 8 8 8 8 8 8 8 8 256*8 256*8 256*8 256*8 256*8 256*8 256*8 256*8 RAM RAM RAM RAM RAM RAM RAM RAM 64 8 8 8 8 8 8 8 8 64 Crossbar- 64 * 1 64 * =1 64 * D-Flipflop Crossbar- Switch Switch 64 * >1 16 RAM 8 RAM RAM 8 RAM 16 64 * >1 64K*8 256*64 256*64 64K*8 64 * >1 16 RAM 8 RAM RAM 8 RAM 16 64 * >1 64K*8 256*64 256*64 64K*8 64 * >1 16 RAM 8 RAM RAM 8 RAM 16 64 * >1 64K*8 256*64 256*64 64K*8 64 * >1 16 RAM 8 RAM RAM 8 RAM 16 64K*8 256*64 256*64 64K*8 September 23rd, 2004 IWSBP2004 8
Definition of the Architecture (2) i nput stage o utp ut stage � The most important step is to map the functionality on a CAM/RAM-structure i 1 o 1 out- input put CAM � The example shows the a RAM i 2 o 2 1 8 lo- mapping of 216 locations 8 lo- c ati- a 2 . . cati- ons of with 12 bit each on the . . 16 ons of . . a 3 12 bits CAM/RAM network using 8 bits eac h locations each i 16 each o 1 2 September 23rd, 2004 IWSBP2004 9
Summary and Outlook (1) � This architecture is very suited for implementation in memory arrays � It comprises very good efficiency in terms of space and energy consumption but low speed September 23rd, 2004 IWSBP2004 10
Summary and Outlook (2) � Open questions: � Which conditions must be met to map a given function on this architecture? � What is the universal architecture for implementing as much functions as possible with some given parameter (e.g. number of in- and outputs) September 23rd, 2004 IWSBP2004 11
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