EFFECT OF SFCL ON DISTRIBUTION POWER QUALITY by Shahram Najafi, - - PowerPoint PPT Presentation
EFFECT OF SFCL ON DISTRIBUTION POWER QUALITY by Shahram Najafi, Prof. Vijay K. Sood , Ahmed Hosny University of Ontario Institute of Technology, Oshawa, Ontario Electrical Power and Energy Conference ( London-Canada) October 2012 1 Outline
by
Shahram Najafi, Prof. Vijay K. Sood, Ahmed Hosny
University of Ontario Institute of Technology, Oshawa, Ontario Electrical Power and Energy Conference (London-Canada) October 2012
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Background
Faults and High Currents
SFCL as a Potential Solution Power Quality
Voltage Sag Harmonic Distortion
Case Study Model and Conditions Simulation Results
Different Fault Types & SFCL Performance Switching Distortion
Conclusion
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Continuous growth of demand resulted in higher fault
current levels
An electrical fault occurs when current flows through an
abnormal or unintended path
Mitigation of fault current levels using newer technology
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Responds
to faults instantaneously, improves power quality, occupies less space, have less power losses in comparison to conventional fault current limiters
Extends the life of many protective devices, more reliable
and allows the usage of existing switchers and circuit breakers
SFCL Operation principals and controller
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Consisting of two or more parallel connected circuit
branches
RC snubber circuit is connected across each power
electronic switch for mitigating the effect rate-of-change
The SFCL is required to have low impedance under
normal conditions but to have high impedance under fault conditions
The speed of the intervention must be high enough
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In normal operating conditions, the
control scheme always triggers the IGBT ON, since modulated output wave (Vm) is higher than the sawtooth waveform (ST) Vm > ST
On
detection
a fault, the conducting IGBT is switched OFF and the fault current is diverted to the limiting impedance since modulated output wave (Vm) is less than the sawtooth waveform (SW) Vm < ST
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PARAMETERS VALUE
Utility Voltage 115 kV Utility Voltage Source Impedance 1% Transformer #1 Voltage 115:15 kV Transformer#1 Power & Impedance 25MVA & 4.5% Transmission Line Z1=0.3101+j0.909 , Z0=0.7186+j4.317
15:4.16 kV Transformer#2 Impedance 20MVA & 9% Load Rating 10MW, 4.16 kV & 0.92 PF lagging
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0.05 sec (3 cycle), and then cleared at 0.0667 sec
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The selection of the reference current is limited to the
pick-up current of over-current relays, and the maximum current interrupting capability of the IGBT
And accordingly limiting impedance Zlim will be designed Using Kirchhoff’s voltage law, the line current through the
SFCL is given by, ....................(1)
9 lim lim −
=
T utility
Z V I
ZT-lim is the total impedance from utility point up to the
load including the point of fault ....(2)
Where, ZTrnsf1+utility is cumulative impedance of transformer# 1 and the utility, ZTransf2 is transformer# 2 impedance, Zload is the load impedance, Zfault is the fault impedance (in this paper the fault is assumed to be bolted with zero impedance)
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] // ) [(
2 1 lim lim fault Transf load utility Trnsf T
Z Z Z Z Z Z + + + =
+ −
But, Ilim is the desired limited maximum faulted current
value during fault ........(3) where, Iratd is the rated current value and ‘desired limited value’ is represented by a number multiplied by the pu rated current value
So, the limiting impedance that will result in desired
limited fault current can be calculated as: ....(4)
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value) limited desired ( *
lim ratd
I I = ]} // ) [( {
2 1 lim lim fault Transf load utility Trnsf T
Z Z Z Z Z Z + + − =
+ −
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Phase “a” current waveform for symmetrical fault at bus B without SFCL; fault inception time = 16.67ms, t = 10s, Zfault =0 Phase “a” line current waveform for symmetrical fault at bus-bar B using SFCL; fault inception time = 16.67 ms, t = 10s, Zfault =0
A three-phase to ground (abc-g) fault with zero fault impedance is
simulated at bus-bar B, just after the SFCL
The Simulated current waveforms through the SFCL components are
presented
ID1-D3 ID2-D4 IIGBT IZnO ILL
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Voltage waveform for symmetrical fault at bus-bar B with the SFCL; fault inception time = 16.67ms, Zfault=0
Voltage magnitude for symmetrical fault) at bus-bar B with/without the SFCL; fault inception time = 33.33ms, Zfault=0
With SFCL Without SFCL
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Although the SFCL provides the desirable current limiting function, it exhibits harmonic characteristics that need to be carefully studied The Total Harmonic Distortion (THD) in the current wave is calculated as 40.11% and that in the voltage is 125%
Per-unit frequency spectrum for phase “a” current in case of symmetrical fault at bus-bar B, Imax = 3.55 kA Per-unit frequency spectrum for phase “a” voltage in case of a symmetrical fault at bus-bar B, Vmax=10.59 kV
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Current waveforms through the SFCL for line-to-ground (a-g) fault at bus-bar B Voltage waveforms for line-to-ground (a-g) fault at bus-bar B Voltage waveforms for line-to-ground (a-g) fault at bus-bar C, fewer switching actions & lower magnitudes
Single phase to ground (the most frequent of occurrence fault in power system) is also shown below
The SFCL has been used and implemented in this paper
using EMTP program to study the impact of SFCL
SFCL
effectively suppressed the fault voltage and mitigated fault current which decrease the short circuit stress on the network
Analyzing transient behavior of the semiconductor switch
assist to improve power quality, to decrease energy dissipation and to reduce the stress on system equipment
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The SFCL however exhibits harmonic generation due to
the switching of the IGBT
Some alternative control circuits to alleviate this problem
are under investigation
In future work, the coordination of the SCFL and the
existing circuit breaker elements in the studied power system will also be investigated
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