DUNE DAQ Data format inside FPGA David Cussans 14 th June 2018 - - PowerPoint PPT Presentation

DUNE DAQ Data format inside FPGA

David Cussans 14th June 2018

Introduction

• Format for data inside FPGAs
• Part of definition of processing blocks.
• Want to run logic ~ 100MHz – 400MHz
• Reuse gates multiple times in single 2MHz ADC sample

time.

• Aim to be able to stream data ( pipelined logic ) where possible
• Rather than read in block, process, transmit
• à Probably (?) implies time-wise ordered data ( sample

1,2,3,4…) , rather than channel-wise data ( channel 1,2,3,…. )

• … but do want some block structure, for transmission to

event builder and , e.g. ease of recovery from lost data.

David Cussans | DAQ Hardware meeting, 14th June 18 2

Hardware Layout

• Look at:
• Combiner/splitter à compression interface
• Compression à Buffer controller interface

To Back- end Data Selection

Diagram – Babak Abi

Trigger Command

David Cussans | DAQ Hardware meeting, 14th June 18

Assumed parameters

• 4 FPGAs per APA
• à 2560 / 4 = 640 wires per APA
• 2MSample/s , 12-bits
• Aim for < 400MHz clock for logic processing
• Try ~ 320MHz processing clock
• à Width of “data bus” = 12 x fsample x Nchan / fclock = 48
• Assume Fibonacci (or some other) encoding(compression) of

sample differences.

• N.B. This is a “straw person” aimed to provoke comment, not

the final word….

David Cussans | DAQ Hardware meeting, 14th June 18 4

Conventions

• Sij = 12-bit Single Phase TPC sample from channel “i” at clock

cycle “j” within a block of data

• For compressed data:
• Pedi = sample value for channel “i” at start of block of data
• Dij = encoded data for channel “i” , clock cycle “j”
• Possibly not DUNE official nomenclature

David Cussans | DAQ Hardware meeting, 14th June 18 5 S1,1 S2,1 S3,1 S4,1 … … … Si,1 S1,2 S2,2 S3,2 S4,2 … … … Si,2 S1,3 S2,3 S3,3 S4,3 … … … Si,3 . . . . . . . . . . . . . . . . . . . . . . . . S1,j S2,j S3,j S4,j … … … Si,j Channel Number ➡ ️ Sample Number ⬇ ️

Raw Data Format

David Cussans | DAQ Hardware meeting, 14th June 18 6

Compressed Data Format

David Cussans | DAQ Hardware meeting, 14th June 18 7 Ped1 Ped2 Ped3 Ped4 Ped5 Ped6 Ped7 Ped8 Ped637 Ped638 Ped639 Ped640 checksum checksum checksum Block #N Timestamp Additional headers ← 48 bits → . .

← 160 clock cycles →

D1,1, D2,1, .. Pedestals for block . . . Compressed deltas, #1

← variable →

.. , D639,1, D640,1, padding D1,2, D2,2, .. Additional checksum , Nsamples . . .. , D639,2, D640,2, padding Compressed deltas, #2 D1,N, D2,N, .. . . .. , D639,N, D640,N, padding . . . . Compressed deltas, #N ………

Conclusion

• Need to define interfaces as part of task of defining processing

blocks.

• For internal data paths, define a format optimized for FPGAs
• Allow for maximum reuse of logic on multiple clock cycles
• Minimize the amount of storage needed for intermediate

results.

• There will also be additional control lines
• E.g. Data-valid strobes
• Run logic ~ 350MHz to allow for headers
• Don’t need an exact multiple of sample frequency – have

strobes.

David Cussans | DAQ Hardware meeting, 14th June 18 8