DU DUNE NE's Hardware Trigger architecture, Su Supern rnova tri - PowerPoint PPT Presentation

DU DUNE NE's Hardware Trigger architecture, Su Supern rnova tri rigger Ba Babak k Ab Abi , Ju Justo Ma Martin-Al Albo DUNE DAQ Simulations Meeting 05 05 Ju Jun 2017 2017 1

Mo Motivations • We have a outline of physics requirements like trigger and rate, compression and zero suppression and other algorithms that need particular hardware resources and architecture. As well ProtoDUNE is going to provide more. • Trigger architecture has important impact on DAQ architecture design. We have to come with minimum facility and hardware requirements that varies triggers need. • Super Nova trigger requirements. • Trigger farm will be subject of other discussion • An internal note will be realised soon with detail of DAQ possible architecture and Cons&Pros 2

DU DUNE NE Gl Global al T Trigger er, Har , Hardwar are & S e & Softwar are s e scheme eme • The current triggers are comprise of following items (at least): 1. Beam spill 2. Atmospherics Muon 3. Supernovae events 4. Proton decay 5. Calibration and random triggers 6. …more?! • The trigger data flow schemes (next slide) can be categorized into three distinct classes regards to hardware and algorithms needed for trigger decision making: 1. Beam and Calibration and random triggers 2. Supernovae trigger ( coming slide details why we consider SN events dissimilar from others in case trigger and impact on DAQ hardware design) 3. Proton decay and Atmospherics Muon triggers 3

Possible architectures genera Po ral diagra rams Front-end TPC Back-end Flange COLD electronics DAQ DAQ Front-end TPC Back-end Flange COLD electronics DAQ DAQ Front-end TPC Back-end Flange COLD electronics DAQ DAQ Read-Out Front-end Back-end TPC A2D DAQ DAQ There is 3 general type of practical architecture diagrams, considering interfacing to existing Cold-electronics and one if Cold-electronics would be removed. 4

DaqD1: DaqD1: RC RCE ba based a d archi hitectur ture 1.Adding additional on board RAM (DDR3/4) in COB to buffer huge data for supernova event. 2.Using capability of interconnection links 5

DaqD2 DaqD2 : : Mi Minimum In In-de detector r ar architecture Timing, Processor unit Off-Detector Detector side trigger,.. FPGA + Buffer side MASTER Time/Clock + Tagging + at Surface distribution compression 1:80 De-MUX ... APA Processor unit 2560 channels Network 100Gb fiber 80:1 MUX 100Gb FPGA + Buffer 100Gb 80 x 1.25Gb serial + Tagging + Links compression ... 150x fiber APA 2Km to surface 2560 channels 80:1 MUX PC- backend DAQ 100Gb 100Gb 80 x 1.25Gb serial Links 150x APA Trigger Processor Farm Trigger Processor Farm 6

DaqD3: Fl DaqD3: Flange e em embed edded ed architec ecture e Off-Detector Timing, Detector side side trigger,.. Time/Clock/ at Surface Trigger distribution APA 4(1) x ZYNQ US+ serial Links IN 2560 channels 32GB DDR4 80 x 1.25Gb Trigger Processor Farm Trigger Processor Farm 100Gb 4x10GE(100GE) DATA 10GE(100GE) 80 x 1.25Gb 124GB DDR4 on Tcp/IP serial Links board 100GE Network PC- backend DAQ APA 4(1) x ZYNQ US+ serial Links IN 2560 channels 32GB DDR4 80 x 1.25Gb 100Gb 4x10GE(100GE) 80 x 1.25Gb 124GB DDR4 on serial Links board Interconnect Network Control/monitor/Data Network 7

DaqD4: DaqD4: Fu Full rea eadout DAQ • In case the worst case scenario if Cold-electronic has to be moved outside of TPC. There would be two architecture (option): • 1- Semi-DaqD2 Flange embedded with digitizer extension. System design/diagram would be the same but choice of FPGA would be wider and cheaper. However need longer R&D. • 2- The Dual Phase has already developed similar architecture, might cooperating with the dual phase is the easiest! approach. 8

TPC TPC Fron ont-en end el elect ectronics cs an and data a fl flow Time/Clock/ Trigger Master -control distribution Timing, trigger,.. 2 2 APA DAQ 1 Flange 2560 channels Main DATA FPGA + CPU 100GE stream Network A Per 1 APA Module Network A 1 Global Global 3 Secondary Network Control/monitor/Data 4 Network B Network B Trigger Processor Farm Trigger Processor Farm 40 SiPMs SSP 10 Photon Detection System per APA 9

Su SuperN rNova Tr Trigger primitives (Oxford scheme) • We propose Trigger primitives (FPGA based) and local event buffer architecture based on Distributed Trigger Processing Farm (DTPF) to reduce the data stream rate. The DTPF performs a number of processing tasks on both front-end DAQ and back-end DAQ with time tagged frames to select candidate events and create trigger signal and information. • Trigger primitives and ring buffer; Supernovae trigger, Requires maximum 10 seconds. Roughly 125GB for a full event buffer scheme (no compression, no tag/headers ) SSP Trigger Processor Farm Global Trigger Trigger Primitive • 10s buffer is independent Generator TPC of how fast our algorithm Trigger Primitive Generator detect a SN event. DAQ has a bandwidth limit that force buffering all SN Data Combiner Front-end Ring Concentrator Electronics before sending off detector Buffer Timing tag Design is based on Cold- • electronics' specs; what if Triggered DATA Board-Reader Event-Builder it's removed ? BACK-END DAQ 10

TRIGGERING SIGNALS 1 Corrected Signal MicroBooNE U Plane, Raw MicroBooNE 0.6 200 V Plane, Raw Y Plane, Raw 0.5 U Plane, Noise-filtered Arbitrary Units 150 ADC Counts V Plane, Noise-filtered 0.4 Y Plane, Noise-filtered 100 0.3 50 0.2 0.1 0 0 0 2000 4000 6000 8000 0 10 20 30 40 50 60 Angle-Corrected PSNR (Peak Signal-to-Noise Ratio) Ticks (0.5us) Worst-case scenario: trigger based on raw signals. 
 Best signal-to-noise ratio for collection wires.

TRIGGERING SIGNALS 2 Alternative Design Alternative Design 50 MeV 98% 20 MeV 96% 50 MeV 91% 10 MeV 87% 20 MeV 79% 5 MeV 74% 10 MeV 54% 5 MeV 33% A. Himmel Using photosensor signals appears more challenging: small signals that depend strongly on detector position.

TRIGGER PRIMITIVES 3 Corrected Signal MicroBooNE 200 150 ADC Counts 100 50 Threshold (dep. on 0 electronics noise) 0 2000 4000 6000 8000 Ticks (0.5us) Trigger primitives: (a few) relevant features of above- threshold signals in collection-plane waveforms. For example: channel number, time length, height, total charge.

NOISE AND BACKGROUND 4 • Electronics noise: sets the detection threshold for trigger primitives. Shouldn’t be a problem except for very low energies (or catastrophic noise levels). • Start with MicroBooNE levels of noise; wait for more info from ProtoDUNE. • Backgrounds (natural radioactivity, cosmogenics, etc.): define rate of fake trigger primitives • How reliable is our current background model? Example: assumed radon levels are 40 mBq/kg, i.e. 20 Rn-222 decays per drift window and APA.

SUPERNOVA TRIGGER ALGORITHM 5 • Energy spectrum • Lousy energy resolution without a t 0 signal. • Track length • Association of trigger primitives from consecutive channels. • Event distribution in time and space • Other?