DU DUNE NE's Hardware Trigger architecture, Su Supern rnova tri - - PowerPoint PPT Presentation

DU DUNE NE's Hardware Trigger architecture, Su Supern rnova tri rigger

Ba Babak k Ab Abi , Ju Justo Ma Martin-Al Albo

DUNE DAQ Simulations Meeting

05 05 Ju Jun 2017 2017

1

Mo Motivations

• We have a outline of physics requirements like trigger and rate,

compression and zero suppression and other algorithms that need particular hardware resources and architecture. As well ProtoDUNE is going to provide more.

• Trigger architecture has important impact on DAQ architecture design. We

have to come with minimum facility and hardware requirements that varies triggers need.

• Super Nova trigger requirements.
• Trigger farm will be subject of other discussion
• An internal note will be realised soon with detail of DAQ possible architecture and

Cons&Pros

2

DU DUNE NE Gl Global al T Trigger er, Har , Hardwar are & S e & Softwar are s e scheme eme

• The current triggers are comprise of following items (at least):

1. Beam spill 2. Atmospherics Muon 3. Supernovae events 4. Proton decay 5. Calibration and random triggers 6. …more?!

• The trigger data flow schemes (next slide) can be categorized into three distinct

classes regards to hardware and algorithms needed for trigger decision making:

1. Beam and Calibration and random triggers 2. Supernovae trigger ( coming slide details why we consider SN events dissimilar from others in case trigger and impact on DAQ hardware design) 3. Proton decay and Atmospherics Muon triggers

3

Po Possible architectures genera ral diagra rams

There is 3 general type of practical architecture diagrams, considering interfacing to existing Cold-electronics and one if Cold-electronics would be removed.

4

Front-end DAQ

TPC

COLD electronics

Flange

Back-end DAQ

Front-end DAQ

TPC

COLD electronics

Flange

Back-end DAQ

TPC

COLD electronics

Flange

Back-end DAQ

Front-end DAQ

TPC

Read-Out A2D

Back-end DAQ

Front-end DAQ

DaqD1: DaqD1: RC RCE ba based a d archi hitectur ture

5

1.Adding additional on board RAM (DDR3/4) in COB to buffer huge data for supernova event. 2.Using capability of interconnection links

DaqD2 DaqD2: : Mi Minimum In In-de detector r ar architecture

6 APA 2560 channels 100Gb 80 x 1.25Gb serial Links PC- backend DAQ 80:1 MUX 100Gb APA 2560 channels 100Gb 80 x 1.25Gb serial Links 80:1 MUX 100Gb 100Gb fiber 150x APA 150x fiber 2Km to surface

Processor unit FPGA + Buffer + Tagging + compression ...

1:80 De-MUX Timing, trigger,.. MASTER Time/Clock distribution

Processor unit FPGA + Buffer + Tagging + compression ...

Network

Detector side Off-Detector side at Surface Trigger Processor Farm Trigger Processor Farm

DaqD3: DaqD3: Fl Flange e em embed edded ed architec ecture e

7

APA 2560 channels 100Gb 80 x 1.25Gb serial Links

PC- backend DAQ

4(1) x ZYNQ US+ 32GB DDR4 4x10GE(100GE) 124GB DDR4 on board

100GE DATA 10GE(100GE) Tcp/IP

Timing, trigger,..

Time/Clock/ Trigger distribution Network

Detector side Off-Detector side at Surface

80 x 1.25Gb serial Links IN

APA 2560 channels 100Gb 80 x 1.25Gb serial Links 4(1) x ZYNQ US+ 32GB DDR4 4x10GE(100GE) 124GB DDR4 on board

80 x 1.25Gb serial Links IN

Network Interconnect Network Control/monitor/Data

Trigger Processor Farm Trigger Processor Farm

DaqD4: DaqD4: Fu Full rea eadout DAQ

• In case the worst case scenario if Cold-electronic has to be moved
• utside of TPC. There would be two architecture (option):
• 1- Semi-DaqD2 Flange embedded with digitizer extension. System

design/diagram would be the same but choice of FPGA would be wider and cheaper. However need longer R&D.

• 2- The Dual Phase has already developed similar architecture, might

cooperating with the dual phase is the easiest! approach.

8

TPC TPC Fron

• nt-en

end el elect ectronics cs an and data a fl flow

9

APA

2560 channels

Global Global

DAQ

FPGA + CPU 100GE Main DATA stream Master -control Timing, trigger,.. Time/Clock/ Trigger distribution Network A Network A Network B Network B Secondary Network Control/monitor/Data Flange Trigger Processor Farm Trigger Processor Farm 2 4 1 2 1 3

40 SiPMs

10 Photon Detection System per APA

SSP

Per 1 APA Module

Su SuperN rNova Tr Trigger primitives (Oxford scheme)

• We propose Trigger primitives (FPGA based) and local event buffer architecture

based on Distributed Trigger Processing Farm (DTPF) to reduce the data stream

• rate. The DTPF performs a number of processing tasks on both front-end DAQ

and back-end DAQ with time tagged frames to select candidate events and create trigger signal and information.

• Trigger primitives and ring buffer; Supernovae trigger, Requires maximum 10
• seconds. Roughly 125GB for a full event buffer scheme (no compression, no

tag/headers )

• 10

Ring Buffer Data Combiner Concentrator Timing tag

TPC Trigger Primitive Generator

Trigger Processor Farm Front-end Electronics Global Trigger Triggered DATA

Board-Reader Event-Builder BACK-END DAQ SSP

Trigger Primitive Generator

Design is based on Cold- electronics' specs; what if it's removed? 10s buffer is independent

• f how fast our algorithm

detect a SN event. DAQ has a bandwidth limit that force buffering all SN before sending off detector

TRIGGERING SIGNALS

1

Ticks (0.5us) 2000 4000 6000 8000 ADC Counts 50 100 150 200

Corrected Signal

MicroBooNE Angle-Corrected PSNR (Peak Signal-to-Noise Ratio)

10 20 30 40 50 60

Arbitrary Units

0.1 0.2 0.3 0.4 0.5 0.6

U Plane, Raw V Plane, Raw Y Plane, Raw U Plane, Noise-filtered V Plane, Noise-filtered Y Plane, Noise-filtered

MicroBooNE

Worst-case scenario: trigger based on raw signals. 
 Best signal-to-noise ratio for collection wires.

TRIGGERING SIGNALS

2

Alternative Design

50 MeV 91% 20 MeV 79% 10 MeV 54% 5 MeV 33%

Alternative Design

50 MeV 98% 20 MeV 96% 10 MeV 87% 5 MeV 74%

• A. Himmel

Using photosensor signals appears more challenging: small signals that depend strongly on detector position.

TRIGGER PRIMITIVES

3

Threshold (dep. on electronics noise)

Ticks (0.5us) 2000 4000 6000 8000 ADC Counts 50 100 150 200

Corrected Signal

MicroBooNE

Trigger primitives: (a few) relevant features of above- threshold signals in collection-plane waveforms. For example: channel number, time length, height, total charge.

NOISE AND BACKGROUND

4

• Electronics noise: sets the detection threshold for

trigger primitives. Shouldn’t be a problem except for very low energies (or catastrophic noise levels).

• Start with MicroBooNE levels of noise; wait for more

info from ProtoDUNE.

• Backgrounds (natural radioactivity, cosmogenics, etc.):

define rate of fake trigger primitives

• How reliable is our current background model?

Example: assumed radon levels are 40 mBq/kg, i.e. 20 Rn-222 decays per drift window and APA.

SUPERNOVA TRIGGER ALGORITHM

5

• Energy spectrum
• Lousy energy resolution without a t0 signal.
• Track length
• Association of trigger primitives from consecutive

channels.

• Event distribution in time and space
• Other?