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Efficient Incremental Flow for signoff- driven ECO
Subramanyam Sripada Song Chen Synopsys Inc. Mar 16, 2017
Agenda
- Background
- Motivation
- Approach
- Results
driven ECO Subramanyam Sripada Song Chen Synopsys Inc. Mar 16, - - PowerPoint PPT Presentation
driven ECO Subramanyam Sripada Song Chen Synopsys Inc. Mar 16, - - PowerPoint PPT Presentation
Efficient Incremental Flow for signoff- driven ECO Subramanyam Sripada Song Chen Synopsys Inc. Mar 16, 2017 Agenda Background Motivation Approach Results Design/Complexity Projections SoC Transistor Count Trend Scenario
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Design/Complexity Projections
1 2 3 4 5 6 7 8 9 10 2013 2014 2015 2016 2017 2018 2019 2020
Billion Transistors
SoC Transistor Count Trend (Logic + SRAM)
Source: ITRS 2013
3X Growth 2015-2020
5 9 10 12 15 7 11 15 24 27
65nm 40nm 28nm 20nm FinFET
Scenario Growth at Advanced Nodes
Modes Corners
Source: Synopsys Customer & Partner Data
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Signoff-driven timing closure
Implementation Timing-driven optimization for critical scenarios hierarchically Signoff-driven ECO Signoff-accurate, physically-aware, all-scenario ECO Place and Route
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Implementation ECO vs Signoff ECO
- Hierarchical vs Flat full-chip
– Implementation ECO is usually done block-level and top-level whereas signoff ECO is typically performed flat but MIM-aware, physically-aware
- Timing scenarios
– Number of timing scenarios is signoff ECO is full combination of modes and corners
- Constraints
– Timing constraints can be different between implementation and signoff
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Multiply Instantiated Modules
- MIM is very common:
– Implementation ECO typically honors MIM as it sees single context – Signoff ECO needs to provide options to honor MIM or break away to meet final timing
- Flat analysis eliminates MIM pessimism
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Motivation
- How to perform signoff ECO with all timing
scenarios on huge (several hundred million instance) designs with high accuracy, efficient runtime, computational resources?
- Efficient incremental flow [this presentation]
- Violation driven circuit reduction [next
presentation]
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Traditional signoff ECO
Parasitic extraction (hierarchical) Signoff STA/ECO (full chip) Place and Route, ECO (hierarchical)
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Previous Attempts
- Previous Attempts:
– All functionality in single process – Perform post-route-ECO with a signoff timer accuracy
- Limited success due to flat analysis on huge
designs
– Additional final flat signoff run
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Incremental signoff ECO
Incremental parasitic extraction (StarRC) Incremental signoff STA and ECO (PrimeTime) Incremental Place and Route (IC Compiler II) 3 1 2
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Incremental signoff ECO
- PrimeTime runs full chip signoff STA
- For each iteration,
- 1. PrimeTime performs physical ECO on all scenarios
- Provides ECO changelist for P&R for each block [2]
- 2. IC Compiler II performs incremental hierarchical P&R
- Provides incremental hierarchical database to StarRC
- 3. StarRC performs incremental hierarchical parasitic
extraction
- Provides incremental SPEF to PrimeTime
- 4. PrimeTime performs incremental full chip signoff
STA
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Incremental signoff ECO
- All communication is done via binary database
– Ascii versions are available for advanced users and for mix-and-match – Incremental SPEF has asymmetric coupling
- All communication ensures data integrity via
signature mechanism
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Results
Design Number
- f
endpoints Outliers > 2ps Outliers > 1% of capture clock period A 22142 39 B 5552 1 C 322364 D 401534 13 E 6240 2 F 2071132 26
3X performance improvement over full STA analysis
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Summary
- There is a great need for optimizing the signoff
ECO process
– With all scenarios, signoff constraints and full-chip
- Proposed a fully incremental signoff ECO