Double Drift in DUNE: Ideas for SP vertical drift CERN, 20/6/2019 - - PowerPoint PPT Presentation

Double Drift in DUNE: Ideas for SP vertical drift

CERN, 20/6/2019

• F. Pietropaolo

ThGEM-like readout in LAr

• Motivation:
• In the past years a dedicated R&D program was started aiming at

replacing the LAr-TPC wire chamber with perforated Multilayer Printer circuit Board, where wires are replaced by copper strips:

• Electrons are 2D focused in the PCB holes
• Strips in the intermediate layer sense an “induction” signal;
• Strips on last plane collect the ionization electrons.
• The idea was driven by several possible improvements wrt wire

chambers:

• the possibility to obtain sharper and better localized induction signals
• the possibility of integrating the FE electronics on the PCB
• the segmentation / modularity
• the possibility to test the full readout before installation.
• The design took advantage of the technological development of wide

area Thick-Gems at CERN.

The concept

4 June 2019 HVS-SP PDR Meeting 3

• Working principle

– Electron trajectories are funneled into holes in plane not in a “slice” like for wires

• PRO:

– Electric field in the hole is uniform. – Bipolar shape of induction signal is more symmetric. – Induction signal is intrinsically larger than with wires and less blurred because the all the weighting field is limited to a single strip and not distributed on several wires – signals shapes are the same on all successive induction layers (same drift field in the holes)

• CONS:

– focusing EF ratio is high (> ratio of hole area to full area) – Capacitance of strips is high (PCB dielectric constant and strip width): higher

• el. noise wrt same length wire

Collection signal Induction signal Unshielded induction

The reference wire case

4 June 2019 HVS-SP PDR Meeting 4

5 10 15 20 25 30 5 10 Drift distance (mm) z-coordinate (0-30 mm) horizontal coordinate (mm) x

• c
• r

d i n a t e ( 1 4 m m ) y-coordinate (12 mm)

20 40 60 80 100 5 10 15 20 25 30

Induction from electron trajectories induction (%) Drift time (us) Trajectory closest to sense wire 1 mm displacement Trajectory closest to adjecent wire

Electric field and equi-induction contours Signal vs distance from wire

The perforated MultiLayer PCB

• Several prototypes have been realized at CERN

for signal test and optimization purposes:

• 1 Screen plane (not read-out)
• 1 induction plane
• 1 collection plane
• Few mm pitch of the read-out strips
• Holes to surface ratio: 30 - 50 %
• Hole positioning not critical (many holes per

strip)

• Hole rim also not critical due to operation in LAr

and absence of amplification

1 mm Ø 0.5 mm Ø 0.7 mm

... ...

Drilled hole Collection layer Induction layer 3.2 mm Grid layer Ind. strip FR4

Early tests B. Baibussinov et al, 2018 JINST 13 T03001

4 June 2019 HVS-SP PDR Meeting 6

• A ML-PCB readout plane was installed and
• perated, exposed at cosmic rays, in a

ICARUS 30 l LAr-TPC at LNL (Italy), 30 cm drift distance:

• Characteristics:

– 96 collection strips + 96 induction strips + a shielding/focusing plane – 3 mm strip pitch – Hole diameter 0.7mm; hole pitch 1mm – Layer separation thickness: 1.6 mm

• It replaced a wire plane with similar pitch for

performance comparison purposes

• The sensing strips read-out:

– ICARUS LNGS version of the warm front end electronics () – through 2m long cables (the dominating input capacitance for the Front End Electronics).

Performance from the test run at LNL

4 June 2019 HVS-SP PDR Meeting 7

• Analysis of cosmic muon

tracks: – Collection signal shape similar to that of wires – Similar S/N (dominated by cable length) – Sharp bipolar Induction signal but too fast for the ICARUS Preamplifier bandwidth and sampling time (0.4 us)

• Further tesr were

envisaged to better

• ptimize induction signals:

– PCB thickness – New FE electronics

Typical signals on a collection (top) and induction (bottom) strips. Drift time Wire coordinate Collection Indiction

Performance from the test run at LNL

4 June 2019 HVS-SP PDR Meeting 8

• dE/dx measurement performed wit

cosmic muons with the same LAr-TPC, equipped with a standard wire chamber gave a reference Most Probable Value value of 5500 e-/mm.

• Scan of voltage across wire planes

was performed to study the electrostatic transparency of the perforated ML-PCB

• The best value of ~5000 e-/mm was

reached at DV=400 V electric bias (limit of the decoupling capacitors)

• For the planned further tests new

decoupling capacitors were foreseen

VGrid (V) VInd (V) VColl (V) MPV signal (e- /mm)

• 220

80 380 4550

• 220

130 480 4800

• 220

180 580 5000

Possible application in DUNE vertical drift

4 June 2019 HVS-SP PDR Meeting 9

• Vertical 6 m Drift LAr-TPC:

– horizontal Cathode at the center

• f

the 12 m long vertical direction, – read-out planes at top and bottom

• The ML-PCB readout could be accommodated in a

simplified supporting structure of the DP CRP detector:

– The ML-PCB replaces the full CRP package – No adjustment motors are required: ML-PCB are in Liquid Phase – Electronics and cabling can sit on the upper surface of the PCB – Connections among adjacent tiles can be performed

• A similar supporting structure could be implemented for

the bottom plane

– Electronic cables could be routed to the top of the cryostat along the membrane walls (far from the HV Field Cage) – Possible issues to be investigated concern the evacuation of the heat of the FE

• The Field cage could be built similarly to the DP case

Design optimization for large surface LAr-TPC

4 June 2019 HVS-SP PDR Meeting 10

• Profiting of the ongoing technological evolution of Thich GEM design and

performance, the CERN PCB workshop can easily produce reliable ML-PCB readout planes with size up to 1m x 0.5 m

• Larger size could be possible from external producers
• The less strict requirements on hole size and rim quality make the production

faster and maybe less expensive that for a ThGEM (presently ~ 2kEuro for a 0.5x 0.5 m2)

• A careful design of the Front End Connectors and location is however

required to minimized dead space at the borders of the plane.

• ML-PCB thickness need optimization mainly focusing on signal shape and

strip capacitance optimization

• The possibility to include a photodetection system, either behind the PCB

(Arapuca?) or integrated in some of the PCB holes (direct SiPM) is also under evaluation

• In the following months we plan to perform a dedicated R&D with the goal of

testing some large size prototypes in the DP cold box at CERN B182, possibly equipped with the present DUNE-SP FE-CE and read-out chain.

Thick-GEM vs perforated ML-PBC