dividing transactional memories by zero
play

Dividing Transactional Memories by Zero Aleksandar Dragojevi - PowerPoint PPT Presentation

Apr 29, 2023 •206 likes •485 views

Dividing Transactional Memories by Zero Aleksandar Dragojevi Rachid Guerraoui Micha Kapaka EPFL, Switzerland Transact 2008 Micha Kapaka (EPFL) STMBench7 Transact 2008 1 / 20 A TM Story TM implementations evaluated with skip

  1. Dividing Transactional Memories by Zero Aleksandar Dragojević Rachid Guerraoui Michał Kapałka EPFL, Switzerland Transact 2008 Michał Kapałka (EPFL) STMBench7 Transact 2008 1 / 20

  2. A TM Story TM implementations evaluated with skip lists, hash tables, … Michał Kapałka (EPFL) STMBench7 Transact 2008 2 / 20

  3. A TM Story TM implementations evaluated with skip lists, hash tables, … Michał Kapałka (EPFL) STMBench7 Transact 2008 2 / 20

  4. A TM Story STMBench7 a benchmark for all TMs Michał Kapałka (EPFL) STMBench7 Transact 2008 3 / 20

  5. A TM Story . Transact 2008 STMBench7 Michał Kapałka (EPFL) TL2, TinySTM . Segmentation fault RSTM . . exception: OutOfMemory . DSTM2 . STMBench7 . 4 / 20

  6. A TM Story . Transact 2008 STMBench7 Michał Kapałka (EPFL) TL2, TinySTM . Segmentation fault RSTM . . exception: OutOfMemory . DSTM2 . STMBench7 . 4 / 20

  7. A TM Story . Transact 2008 STMBench7 Michał Kapałka (EPFL) TL2, TinySTM . Segmentation fault RSTM . . exception: OutOfMemory . DSTM2 . STMBench7 . 4 / 20

  8. A TM Story . Transact 2008 STMBench7 Michał Kapałka (EPFL) TL2, TinySTM . Segmentation fault RSTM . . exception: OutOfMemory . DSTM2 . STMBench7 . 4 / 20

  9. A TM Story . Transact 2008 STMBench7 Michał Kapałka (EPFL) TL2, TinySTM . Segmentation fault RSTM . . exception: OutOfMemory . DSTM2 . STMBench7 . 4 / 20

  10. A TM Story . Transact 2008 STMBench7 Michał Kapałka (EPFL) TL2, TinySTM . Segmentation fault RSTM . . exception: OutOfMemory . DSTM2 . STMBench7 . 4 / 20

  11. ? Michał Kapałka (EPFL) STMBench7 Transact 2008 5 / 20

  12. The Goal of STMBench7 Test performance and usability Michał Kapałka (EPFL) STMBench7 Transact 2008 6 / 20

  13. My Goal Today Show that STMBench7 is a valuable tool for measuring performance & usability of TMs Michał Kapałka (EPFL) STMBench7 Transact 2008 7 / 20

  14. Outline 1 STMBench7 2 Performance results examples Michał Kapałka (EPFL) STMBench7 Transact 2008 8 / 20

  15. The STMBench7 Benchmark for TMs Real-world workload Transact 2008 STMBench7 Michał Kapałka (EPFL) throughput Latency, . op3 . structure Data . Thread 3 . Thread 2 . Thread 1 . . operations Various-length dynamic structure Large, complex & (CAD/CAM/…) 9 / 20 op1 . op2 . ⇓

  16. STMBench7 Main Tree Assemblies . … . 7 levels . Complex (CA) . . Base Assemblies (BA) Michał Kapałka (EPFL) STMBench7 Transact 2008 BA BA . CA . . Module . Manual . CA . CA . . CA . … . … . … 10 / 20

  17. STMBench7 Design Library . … . … . Base Assemblies (BA) Composite Parts . (CP) . Atomic Parts (AP) . Michał Kapałka (EPFL) STMBench7 Transact 2008 . AP Graph . . . BA . … . BA CP Doc . CP . … . CP . 11 / 20 + indexes

  18. STMBench7 Features Large data structure unforgiving for large per-object overheads Short and long operations “explode” non-linear algorithms Complex access patterns test policies, not only raw performance Complex objects, inheritance OO features check Use of standard libraries usability test Michał Kapałka (EPFL) STMBench7 Transact 2008 12 / 20

  19. Outline 1 STMBench7 2 Performance results examples Michał Kapałka (EPFL) STMBench7 Transact 2008 13 / 20

  20. Lock-Based vs. Obstruction-Free Urban legend: obstruction-free TMs inherently slow lock-based TMs much faster Michał Kapałka (EPFL) STMBench7 Transact 2008 14 / 20

  21. Lock-Based vs. Obstruction-Free Threads . 8 . 4 . 1 . . . kTx / s . . . . . . . 16 24 . . Transact 2008 STMBench7 Michał Kapałka (EPFL) . TinySTM . RSTM TL2 . . 4 . 3 . 2 . 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 / 20 4 × 2-core Opteron

  22. Contention Management Contention management and Conflict detection mechanism How are those connected? Michał Kapałka (EPFL) STMBench7 Transact 2008 16 / 20

  23. Contention Management . 4 . 1 . Threads . kTx / s . . . 8 . . . . . . . . . . . . . eager Greedy Transact 2008 STMBench7 Michał Kapałka (EPFL) lazy Greedy . lazy Polka . eager Polka . . 16 4 . 3 . 2 . 1 . 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 / 20

  24. Contention Management . 4 . 1 . Threads . kTx / s . . . 8 . . . . . . . . . . . . . eager Greedy Transact 2008 STMBench7 Michał Kapałka (EPFL) lazy Greedy . lazy Polka . eager Polka . . 16 4 . 3 . 2 . 1 . 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 / 20

  25. Performance: General Observation Policy Per-access overhead Michał Kapałka (EPFL) STMBench7 Transact 2008 18 / 20 >

  26. Summary STMBench7 a benchmark for all TMs Evaluate performance & usability in a (possibly) realistic setting (and discover bugs…) Michał Kapałka (EPFL) STMBench7 Transact 2008 19 / 20

  27. STMBench7 lpd.epfl.ch/site/research/tmeval free (BSD-style license) Michał Kapałka (EPFL) STMBench7 Transact 2008 20 / 20

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

Verification of Transactional Memories that support Non-Transactional Memory Accesses Ariel Cohen

Verification of Transactional Memories that support Non-Transactional Memory Accesses Ariel Cohen

Verification of Transactional Memories that support Non-Transactional Memory Accesses Ariel Cohen 1 , Amir Pnueli 1 , and Lenore Zuck 2 1 New York University 2 University of Illinois at Chicago TRANSACT February 2008 Cohen, Pnueli, Zuck

665 views • 28 slides
Arrays and Picture Models Dividing by 4 Dividing by 5 Dividing by 6 Dividing by 7

Arrays and Picture Models Dividing by 4 Dividing by 5 Dividing by 6 Dividing by 7

Slide 1 / 168 Slide 2 / 168 3rd Grade Division 2015-11-03 www.njctl.org Slide 3 / 168 Slide 4 / 168 Table of Contents Click on a topic to Arrays and Pictures go to that section. Using Multiplication Dividing by 1 Dividing by 2

572 views • 44 slides
Transactional Memories: a theoretical introduction Selim Arsever & Pascal Perez Shared

Transactional Memories: a theoretical introduction Selim Arsever & Pascal Perez Shared

Transactional Memories: a theoretical introduction Selim Arsever & Pascal Perez Shared Memory Problems M(w,r,v) := w(f).M<w,r,f> + r<v>.M<w,r,v> A(w,r) := w<v>.WORK.r(v').[v'=v].A A<w,r> | A<w,r> |

624 views • 40 slides
Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA

Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA

Memories Introduction Why do we need memory in an FPGA Device? Topics Types of FPGA Memories Available Resources Realizing memories in an HDL design Applications Examples Extra: Memory Controller Block Memories

692 views • 10 slides
Real Time Embedded Systems " Memories Memories " rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL

Real Time Embedded Systems " Memories Memories " rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL

Real Time Embedded Systems " Memories Memories " rene.beuchat@epfl.ch LAP/ISIM/IC/EPFL Charg de cours LSN/hepia Prof. HES 1998-2008 R.Beuchat / Memories 2 General classification of electronic memories Non-volatile

1.13k views • 86 slides
Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory

Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory

Introduction Methodology Performance Evaluation Conclusions References Evaluating the Impact of Transactional Characteristics on the Performance of Transactional Memory Applications 1 Fernando Rui, 2 Mrcio Castro, 1 Dalvan Griebler, 1 Luiz

370 views • 16 slides
A Suitcase full of memories: Exploring the meaning of tourism memories for people with dementia

A Suitcase full of memories: Exploring the meaning of tourism memories for people with dementia

A Suitcase full of memories: Exploring the meaning of tourism memories for people with dementia and their partners: reconnecting through the past. Jane Mullins (RGN, BN, PGCASR ) PhD Candidate School of Management Supervisors: Dr Diane

154 views • 14 slides
Transactional Memory 1 To read more This days papers: Herlihy and Moss, Transactional

Transactional Memory 1 To read more This days papers: Herlihy and Moss, Transactional

Transactional Memory 1 To read more This days papers: Herlihy and Moss, Transactional Memory: Architectural Support for Lock-Free Data Structures McKenney et al, Why The Grass May Not Be Greener On The Other Side: A Comparison

719 views • 41 slides
NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 27 November 2015 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 27 November 2015 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 27 November 2015 Lecture 8 Problems with locks Atomic blocks and composition Hardware transactional memory Software transactional memory Transactional

1.42k views • 93 slides
NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 25 November 2016 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 25 November 2016 Lecture 8

NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 25 November 2016 Lecture 8 Problems with locks Atomic blocks and composition Hardware transactional memory Software transactional memory Transactional

1k views • 89 slides
Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

456 views • 21 slides
Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!!

Memories and SRAM 1 Silicon Memories Why store things in silicon? Its fast!!! Compatible with logic devices (mostly) The main goal is to be cheap Dense -- The smaller the bits, the less area you need, and the more bits you

241 views • 22 slides
Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions

Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions

Extending Hardware Transactional Memory to Support Non-busy Waiting and Non-transactional Actions Craig Zilles and Lee Baugh University of Illinois at Urbana-Champaign paper available at: http:/

453 views • 19 slides
LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories Hsin-Jung Yang ,

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories Hsin-Jung Yang ,

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories Hsin-Jung Yang , Kermin E. Fleming , Michael Adler , and Joel Emer Massachusetts Institute of Technology Intel Corporation May 12th, FCCM 2014

617 views • 48 slides
Transactional Systems: Examples Core OS / RedHat: Various: SUSE: Common Properties of

Transactional Systems: Examples Core OS / RedHat: Various: SUSE: Common Properties of

Transactional Systems: Examples Core OS / RedHat: Various: SUSE: Common Properties of Transactional Systems Transactional / atomic updates Read-only root file system Focus on large deployments (clouds) or embedded systems

814 views • 36 slides
Eric Berne 1910 - 1970 Transactional Analysis UET6 TASK 02 Transactional Analysis is: A

Eric Berne 1910 - 1970 Transactional Analysis UET6 TASK 02 Transactional Analysis is: A

Eric Berne 1910 - 1970 Transactional Analysis UET6 TASK 02 Transactional Analysis is: A Extra-Freudian form of psychoanalytical theory, which examines human behaviour and communication. Not about the study of the subconsciousness, but the

417 views • 7 slides
Patchable (Indistinguishability) Obfuscation: iO for evolving software Prabhanjan Abhishek

Patchable (Indistinguishability) Obfuscation: iO for evolving software Prabhanjan Abhishek

Patchable (Indistinguishability) Obfuscation: iO for evolving software Prabhanjan Abhishek Amit Ananth Jain Sahai Software Evolution 1990 Software Evolution 1990 1995 Software Evolution 1997 1990 1995 Software Evolution 1997 1990

1.03k views • 78 slides
Science (Bridging Course) Turing Machines Gian Diego Tipaldi Topics Covered Turing machines

Science (Bridging Course) Turing Machines Gian Diego Tipaldi Topics Covered Turing machines

Theoretical Computer Science (Bridging Course) Turing Machines Gian Diego Tipaldi Topics Covered Turing machines Variants of Turing machines Multi-tape Non-deterministic Definition of algorithm The Church-Turing Thesis

962 views • 48 slides
Next Towards undecidability: The Halting Problem Countable and uncountable infinities

Next Towards undecidability: The Halting Problem Countable and uncountable infinities

CSE 2001: Introduction to Theory of Computation Summer 2013 Week 10: Decidability Part 2 Yves Lesprance Course page: http://www.cse.yorku.ca/course/2001 Slides are mostly taken from Suprakash Dattas for Winter 2013; some slides are adapted

561 views • 21 slides
l*.P w /V* \JI L "")"*)U AttllA4 ryb (^ A) YA N-,;k "t\ -'^fu-

l*.P w /V* \JI L "")"*)U AttllA4 ryb (^ A) YA N-,;k "t\ -'^fu-

G"^;^n"^ l GC"+l'1-11""1 ffJ \^it.i ^, tl* ,"AhA N";i N"t ^^XW- -h^ vr-/,i --,D}1 \ *o,oo, u* +"F*" ^ \i{ ?xt\ \ " A*" 'D*'A"^k J ' .r\ ('\ \ I ) \----' )zo o\ lt \= (zh})

456 views • 10 slides
CS 301 Lecture 22 Mapping reductions Stephen Checkoway April 18, 2018 1 / 41 Review of

CS 301 Lecture 22 Mapping reductions Stephen Checkoway April 18, 2018 1 / 41 Review of

CS 301 Lecture 22 Mapping reductions Stephen Checkoway April 18, 2018 1 / 41 Review of decidable languages Context-free languages (and thus regular) 2 / 41 Review of decidable languages Context-free languages (and thus regular)

1.5k views • 100 slides
Turing Machines (TM) Deterministic Turing Machine (DTM) Nondeterministic Turing Machine

Turing Machines (TM) Deterministic Turing Machine (DTM) Nondeterministic Turing Machine

Turing Machines (TM) Deterministic Turing Machine (DTM) Nondeterministic Turing Machine (NDTM) 1 Deterministic Turing Machine (DTM) .. .. B B 0 1 1 0 0 B B Finite Control Two-way, infinite tape, broken into

616 views • 14 slides
USTRANSCOM Initiatives A Financial Perspective Mr. Dan McMillin USTRANSCOM J8 22 Oct 2018

USTRANSCOM Initiatives A Financial Perspective Mr. Dan McMillin USTRANSCOM J8 22 Oct 2018

UNCLASSIFIED USTRANSCOM Initiatives Financial Perspective USTRANSCOM Initiatives A Financial Perspective Mr. Dan McMillin USTRANSCOM J8 22 Oct 2018 Together, we deliver. 1 UNCLASSIFIED UNCLASSIFIED USTRANSCOM Initiatives- A Financial

217 views • 18 slides
Naturality for Free The category interpretation of directed type theory Thorsten Altenkirch,

Naturality for Free The category interpretation of directed type theory Thorsten Altenkirch,

Naturality for Free The category interpretation of directed type theory Thorsten Altenkirch, Filippo Sestini Functional Programming Laboratory School of Computer Science University of Nottingham Homotopy Type Theory 2019 Thorsten Altenkirch,

540 views • 38 slides

More recommend