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Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems
Viaceslav Izosimov, Paul Pop, Petru Eles, Zebo Peng Embedded Systems Lab (ESLAB) Linköping University, Sweden
Design Optimization of Time- and Cost-Constrained Fault-Tolerant - - PowerPoint PPT Presentation
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Distributed Embedded Systems Viaceslav Izosimov, Paul Pop, Petru Eles, Zebo Peng Embedded Systems Lab (ESLAB) Linkping University, Sweden 1/21 1 of 14 Motivation Faults
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Viaceslav Izosimov, Paul Pop, Petru Eles, Zebo Peng Embedded Systems Lab (ESLAB) Linköping University, Sweden
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S1 S3 S2 S4 S1 S3 S2 S4 TDMA Round Cycle of two rounds Slot
time-division multiple-access (TDMA)
controller: message descriptor list (MEDL)
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Application: set of process graphs Architecture: time-triggered system
Fault-model: transient faults
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P1 N1: S1 N2: S11 N3: S14 P2 P4 P5 P3 m1 m2
2 P2 P4 P3 P5 P1 m1 m2
N1 N2 N3
S11 S12 S13 P1 P1 N2 S1 S2 S3 P2 P2 S4 P3 S5 S6 S7 S8 S10 S9 P4 P3 P4 P3 P4 P4 N1 S14 S15 S18 P5 P5 N3
Root schedules
P1 N1: S2 N2: S12 N3: S14 P2 P4 P5 P3 m1 m2 P1
Contingency schedules
S1 S11 S2 S12
P2
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N1 N2
P1 P3 P2 m1 1 P1 P2 P3 N1 N2 40 50 40 60 50 70
N1 N2 TTP P1 P2
S1S2
P3 Met
A1
N1 N2 TTP P1 P2 P3
S1S2
Missed P1 N1 N2 TTP P1 P2 P2 P3 P3
S1S2
m1 m1 m2 m2
Deadline Met P1 P3 P2 m1 m2 A2
P1
S1
N1 N2 TTP P1
S2
P2 P2 P3 P3 Deadline Missed
m1 m1
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P1 N1 N2 TTP P2 P3
S1S2
P4
m2
Missed
P1 P2 P3 N1 N2 40 50 60 60 80 80 P4 40 50 1
N1 N2
P1 P4 P2 P3 m1 m2 m3
P1 N1 N2 TTP P2 P3
S1S2
m2
P4 P1 N1 N2 TTP P2 P3
S1S2
m2
P4
Deadline
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P1 N1 N2 TTP P2 P3
S1S2
P4
m2
Missed
P1 P2 P3 N1 N2 40 50 60 60 80 80 P4 40 50 1
N1 N2
P1 P4 P2 P3 m1 m2 m3
P1 N1 N2 TTP P2 P3
S1S2
m2
P4 N1 N2 P1 P3
S1S2
P4 P2 P1
m1 m1
TTP
m2 m2
P2
m3 m3
P3 P4 Missed P1 N1 N2 TTP P2 P3
S1S2
m2
P4
Deadline
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P1 N1 N2 TTP P2 P3
S1S2
P4
m2
Missed
P1 P2 P3 N1 N2 40 50 60 60 80 80 P4 40 50 1
N1 N2
P1 P4 P2 P3 m1 m2 m3
P1 N1 N2 TTP P2 P3
S1S2
m2
P4 N1 N2 P1 P3
S1S2
P4 P2 P1
m1 m1
TTP
m2 m2
P2
m3 m3
P3 P4 Missed P1 N1 N2 TTP P2 P3
S1S2
m2
P4
N1 N2 P1 P3
S1S2
P4 P2 P1
m2 m1
TTP Met
Deadline
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P1 P4 P2 P3 m1 m2 m3 m4 P1 P2 P3 P4 N1 N2 40 X 60 60 40 70 X 70 1
N1 N2
P1 N1 N2 TTP P2 P3
S1S2
m2
P4
m4
Best mapping without considering fault-tolerance
Deadline Missed P1 N1 N2 TTP P2 P3
S1S2
P4
m4 m2
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P1 P4 P2 P3 m1 m2 m3 m4 P1 P2 P3 P4 N1 N2 40 X 60 60 40 70 X 70 1
N1 N2
P1 N1 N2 TTP P2 P3
S1S2
m2
P4
m4
Best mapping without considering fault-tolerance
Deadline Missed P1 N1 N2 TTP P2 P3
S1S2
P4
m4 m2
P1 N1 N2 TTP P2 P3
S1S2
m4 m2
P4 Deadline Met
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P1 P2 P3 N1 N2 40 50 60 60 75 75 P4 40 50 1 N1 N2
P1 P4 P2 P3 m1 m2 m3
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 P4 P2
m1
1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
S1
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P1 P2 P3 N1 N2 40 50 60 60 75 75 P4 40 50 1 N1 N2
P1 P4 P2 P3 m1 m2 m3
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 P4 P2
m1
1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
S1 N1 N2 P1 P3 S1S2 P4 P2 P1
m2 m1
TTP 1 2 Wait 1 2 Tabu P4 P3 P2 P1 1 2 Wait 1 2 Tabu P4 P3 P2 P1
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P1 P2 P3 N1 N2 40 50 60 60 75 75 P4 40 50 1 N1 N2
P1 P4 P2 P3 m1 m2 m3
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 P4 P2
m1
1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
S1 N1 N2 P1 P3 S1S2 P4 P2 P1
m2 m1
TTP 1 2 Wait 1 2 Tabu P4 P3 P2 P1 1 2 Wait 1 2 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
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P1 P2 P3 N1 N2 40 50 60 60 75 75 P4 40 50 1 N1 N2
P1 P4 P2 P3 m1 m2 m3
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 P4 P2
m1
1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
S1 N1 N2 P1 P3 S1S2 P4 P2 P1
m2 m1
TTP 1 2 Wait 1 2 Tabu P4 P3 P2 P1 1 2 Wait 1 2 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 P3 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
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P1 P2 P3 N1 N2 40 50 60 60 75 75 P4 40 50 1 N1 N2
P1 P4 P2 P3 m1 m2 m3
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 P4 P2
m1
1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
S1 N1 N2 P1 P3 S1S2 P4 P2 P1
m2 m1
TTP 1 2 Wait 1 2 Tabu P4 P3 P2 P1 1 2 Wait 1 2 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 TTP P1 P3 S1S2 S2 P4
m2
P2 P3 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1 1 1 1 Wait 2 1 Tabu P4 P3 P2 P1
N1 N2 P1 P3 S1S2 P4 P2 P1
m2 m1
TTP 1 2 Wait 1 2 Tabu P4 P3 P2 P1 1 2 Wait 1 2 Tabu P4 P3 P2 P1
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