DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 1/26 Design and Modeling of a 0.4mW/Ch Multi-Channel Integrated Circuit for Infrared Gas Recognition S. Sutula, C. Ferrer and F. Serra-Graells stepan.sutula@imb-cnm.csic.es Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC) November 2010 S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 2/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 3/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
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DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 5/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 6/26 ROIC Channel Architecture ◮ High programmability f c (2bit) progin I bias (2bit) Config. event Register ◮ No external progout + V th components G m (2bit) G (2bit) C int 1 (� bit) V amp up datain V int ◮ Built-in bias V sens 20bit event R sens Counter I eff dataout generators for low down Bias & ref. - V th generator crosstalk A/D Converter ◮ Digital only interface V com V blind V lockin ◮ External lock-in synchronization ∆ V sens = I bias ∆ R sens ◮ Dedicated blind channel for cancellation of common disturbing signals ◮ Individual configuration register per channel S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 7/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 8/26 Pre-Amplification and Filtering ◭ Sub-Hz high-pass specs I tun V tun ◭ Independent gain and corner M2 P £ programmability required M1 ◮ Highly linear cap amplifier: C B G = ∆ V amp ∆ V sens = C A C B init ◮ Subthreshold MRC filtering: C A V sens V amp I tun ( PTAT ) f co = 1 − Vcorner f c = f co e Ut 2 π C B U t ◮ Fast initialization switch + V corner V ref S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 9/26 Pre-Amplification and Filtering ◮ Gain tuning by P scaling I tun V tun ◮ Multi-decade filter log tuning: M2 P £ V corner = M ∆ V corner = MU t ln ( NK ) M1 f co f c = ( NK ) M C B f c × 10 ± 3 ⇔ V corner ± 173mV at 25 o C init 1 : N 1 : N C A V sens V amp M £ M1 M2 1 V ref K 1 K + V corner V ref ¢ V corner V corner S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 10/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 11/26 Blind Cancellation and Lock-in Demodulation ◮ Differential to single ended M7 M8 ◮ Voltage-to- current conversion I ota ◮ Lock-in demodulation I eff V amp V blind M1 M2 + V ref ◮ Low-power subthreshold OTA : PDM stage V lockin of the ADC ∆ V amp = I ota I eff G m = 2 nU t ∝ U t M4 M3 M5 M6 I ota ∝ I S = 2 n β U 2 t (cascode topology not shown) ◮ Current-domain lock-in demodulation by cross-coupling ◮ Voltage log compression allows fast switching at low-power S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 12/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 13/26 Integrating A/D Conversion event ◮ PDM noise shaping + V th C int 1 (� bit) ◮ Digital counter as low-pass filter up datain V int 20bit event Counter ◮ Asynchronous operation for very I eff dataout down low-power and low-crosstalk - V th Pulse density modulation Digital filtering S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 14/26 Integrating A/D Conversion init ◮ PDM noise shaping C int V ref + V th ◮ Digital counter as low-pass filter I eff up V int ◮ Asynchronous operation for very event low-power and low-crosstalk event down ◮ Loss-less analog integrator with CDS C reset CDS / V - V ref th for high-linearity and noise reduction: V ref I eff f PDM = C int V th S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 15/26 Integrating A/D Conversion init ◮ PDM noise shaping C int V ref + V th ◮ Digital counter as low-pass filter I eff up V int ◮ Asynchronous operation for very event low-power and low-crosstalk event down ◮ Loss-less analog integrator with CDS C reset CDS / V - V ref th for high-linearity and noise reduction: V ref I eff f PDM = V ref C int V th M1 M3 ◮ Built-in threshold comparator: up down V th = nU t ln X M4 M5 1 X X 1 ◮ Thermal compensation of G m : V int n adc = T samp f PDM = C A G m T samp q adc = ⌊ n adc ⌋ C int ∆ R sens C B V th S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 16/26 1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 17/26 Post Layout High Level Modeling ◮ Simulation time reduction Up Up DataOut 1 1 Vsens Vamp Vamp Ieff DataOut Vsens ◮ Complete read-out Preamplifier Down Overflow Down 2 2 Vblind Ieff Ieff Overflow channel model Vint Vint Digital Vblind event event Filter 3 Vlockin ◮ Entire set of channel Integrator PDM Vlockin Lock-in Demodulator configurations S. Sutula et al. IMB-CNM(CSIC)
DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 18/26 Post Layout High Level Modeling ◮ Simulation time reduction Up Up DataOut 1 1 Vsens Vamp Vamp Ieff DataOut Vsens ◮ Complete read-out Preamplifier Down Overflow Down 2 2 Vblind Ieff Ieff Overflow channel model Vint Vint Digital Vblind event event Filter 3 Vlockin ◮ Entire set of channel Integrator PDM Vlockin Lock-in Demodulator configurations ◮ Wide range of nonidealities White Noise modeling H_n ◮ Technology process Noise Modeling 1/w_ns+1 and temperature s 1 ◮ Flicker and thermal 1 A 1 s+w_h 1/w_ls+1 Vsens Vamp Output noise options High -Pass Low-Pass Gain Range Vdc Limit ◮ External sensor DC Output Level modeling S. Sutula et al. IMB-CNM(CSIC)
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