Design and Modeling of a 0.4mW/Ch Multi-Channel Integrated Circuit - - PowerPoint PPT Presentation

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Design and Modeling of a 0.4mW/Ch Multi-Channel Integrated Circuit - - PowerPoint PPT Presentation

Jan 03, 2023 273 likes •546 views

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 1/26 Design and Modeling of a 0.4mW/Ch Multi-Channel Integrated Circuit for Infrared Gas Recognition S. Sutula, C. Ferrer and F. Serra-Graells

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SLIDE 1

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 1/26

Design and Modeling of a 0.4mW/Ch Multi-Channel Integrated Circuit for Infrared Gas Recognition

  • S. Sutula, C. Ferrer and F. Serra-Graells

stepan.sutula@imb-cnm.csic.es Integrated Circuits and Systems (ICAS) Instituto de Microelectrónica de Barcelona, IMB-CNM(CSIC)

November 2010

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 2

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 2/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 3

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 3/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 4

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 4/26

Introduction

◮ Real-time gas recognition for

environmental monitoring, toxic gas detection. . .

◮ IR spectroscopic absorption

digital fingerprint

◮ Thermal µbolometer LWIR

sensing array ◮ Multi-channel ROIC for fast acquisition and low-noise ◮ Channel lock-in demodulation for high-accuracy ◮ Low-power operation to avoid thermal drifts of IR sensors ◮ Compact pitch for direct sensors-ROIC bonding

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 5

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 5/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 6

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 6/26

ROIC Channel Architecture

Vsens Vamp Ieff Vlockin Gm(2bit) Cint 1

( bit)

fc(2bit) G(2bit) Vblind

event

Vint

up

20bit Counter

event

Ibias(2bit) A/D Converter

Bias & ref. generator Config. Register

progin dataout down

Vcom +Vth

  • Vth

progout datain

Rsens

◮ External lock-in synchronization ◮ Dedicated blind channel for cancellation of

common disturbing signals

◮ Individual configuration register per channel

◮ High programmability ◮ No external components ◮ Built-in bias generators for low crosstalk ◮ Digital only interface ∆Vsens = Ibias∆Rsens

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 7

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 7/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 8

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 8/26

Pre-Amplification and Filtering

◭ Sub-Hz high-pass specs ◭ Independent gain and corner programmability required ◮ Highly linear cap amplifier: G = ∆Vamp ∆Vsens = CA CB ◮ Subthreshold MRC filtering: fc = fcoe

− Vcorner

Ut

fco = 1 2π Itun(PTAT) CBUt ◮ Fast initialization switch

CB Vref Vsens CA Vamp Vcorner Vtun

+

Itun

M2 M1

P£

init

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 9

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 9/26

Pre-Amplification and Filtering

◮ Gain tuning by P scaling ◮ Multi-decade filter log tuning: Vcorner = M∆Vcorner = MUt ln (NK) fc = fco (NK)M fc ×10±3 ⇔ Vcorner ±173mV at 25oC

M2 M1

1 N : K 1 Vref 1 N : K 1 ¢Vcorner M£ Vcorner

CB Vref Vsens CA Vamp Vcorner Vtun

+

Itun

M2 M1

P£

init

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 10

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 10/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 11

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 11/26

Blind Cancellation and Lock-in Demodulation

◮ Differential to single ended ◮ Voltage-to-current conversion ◮ Lock-in demodulation

◮ Low-power subthreshold OTA: Gm = Ieff ∆Vamp = Iota 2nUt ∝ Ut Iota ∝ IS = 2nβU 2

t

◮ Current-domain lock-in demodulation by cross-coupling ◮ Voltage log compression allows fast switching at low-power

Vamp Iota

M3 M4 M1 M2

Vblind

M5 M6

Ieff

M7 M8

Vlockin

+

Vref

PDM stage

  • f the ADC

(cascode topology not shown)

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 12

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 12/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 13

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 13/26

Integrating A/D Conversion

◮ PDM noise shaping ◮ Digital counter as low-pass filter

◮ Asynchronous operation for very low-power and low-crosstalk

Ieff Cint 1

( bit) event

Vint

up

20bit Counter

event

Pulse density modulation

dataout down

+Vth

  • Vth

datain

Digital filtering

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 14

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 14/26

Integrating A/D Conversion

◮ PDM noise shaping ◮ Digital counter as low-pass filter

◮ Asynchronous operation for very low-power and low-crosstalk ◮ Loss-less analog integrator with CDS for high-linearity and noise reduction: fPDM = Ieff CintVth

Vint Cint Vref Creset CDS

/

Ieff V V

ref th

  • up

event down

Vref+Vth

event init

  • S. Sutula et al.

IMB-CNM(CSIC)

slide-15
SLIDE 15

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 15/26

Integrating A/D Conversion

◮ PDM noise shaping ◮ Digital counter as low-pass filter

◮ Asynchronous operation for very low-power and low-crosstalk ◮ Loss-less analog integrator with CDS for high-linearity and noise reduction: fPDM = Ieff CintVth ◮ Built-in threshold comparator: Vth = nUt ln X ◮ Thermal compensation of Gm: qadc = ⌊nadc⌋ nadc = TsampfPDM = CA CB Gm Vth Tsamp Cint ∆Rsens

Vint Cint Vref Creset CDS

/

Ieff V V

ref th

  • up

event down

Vref+Vth

event init

Vint

up down

Vref

M5 M4

X 1 X 1

M1 M3

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 16

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 16/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 17

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 17/26

Post Layout High Level Modeling

◮ Simulation time reduction ◮ Complete read-out channel model ◮ Entire set of channel configurations

Overflow 2 DataOut 1 Preamplifier Vsens Vamp PDM Ieff Vint Up Down event Lock-in Demodulator Vamp Vblind Vlockin Ieff Integrator Ieff event Vint Digital Filter Up Down DataOut Overflow Vlockin 3 Vblind 2 Vsens 1

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 18

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 18/26

Post Layout High Level Modeling

◮ Simulation time reduction ◮ Complete read-out channel model ◮ Entire set of channel configurations ◮ Wide range of nonidealities modeling

◮ Technology process

and temperature

◮ Flicker and thermal

noise options

◮ External sensor

modeling

Overflow 2 DataOut 1 Preamplifier Vsens Vamp PDM Ieff Vint Up Down event Lock-in Demodulator Vamp Vblind Vlockin Ieff Integrator Ieff event Vint Digital Filter Up Down DataOut Overflow Vlockin 3 Vblind 2 Vsens 1 DC Output Level Vamp 1 White Noise Output Range Limit Noise Modeling H_n 1/w_ns+1 Low-Pass 1 1/w_ls+1 High -Pass s s+w_h Gain A Vdc Vsens 1

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 19

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 19/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 20

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 20/26

CMOS Integration and Experimental Results

◮ 0.35µm 2P4M CMOS

channel module test chip

◮ Main design parameters:

CA = 20pF CB = {0.1, 0.2, 0.4, 1}pF K = 10 N = {1, 11} M = 3 Itun = 100nA Iota = {1, 2, 5, 10}µA Vth = 120mV Tpulse = 500ns

10fullchannels forcrosstalkstudy blind channel channel blocks sensor bias high-pass pre-amp referencegenerator PDM config. register async. counter 100 m ¹

◮ Access to intermediate stages

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 21

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 21/26

CMOS Integration and Experimental Results

◮ Sub-Hz pre-amplifier independent tuning (16 configurations)

Frequency [Hz] 100k 10k 1k 100 10 1 0.1

  • 30
  • 20
  • 10

10 20 30 40 50

gain<1:0>=00 01 10 11 corner<1:0>=00 01 10 11

  • 30
  • 20
  • 10

10 20 30 40 50 j j ¢ /¢ V V

amp sens [dB]

j j ¢ /¢ V V

amp sens [dB]

  • S. Sutula et al.

IMB-CNM(CSIC)

slide-22
SLIDE 22

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 22/26

CMOS Integration and Experimental Results

◮ Sub-Hz pre-amplifier independent tuning (16 configurations) ◮ Highly linear PDM up to pulse width hard limit

100

transc<1:0>=00 01 10 11

¢ [mV] Vamp 10 1 0.1 1M 100k 10k 1k

1 2Tpulse

fPDM [Hz]

for cint<0>=0

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 23

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 23/26

CMOS Integration and Experimental Results

◮ Sub-Hz pre-amplifier independent tuning (16 configurations) ◮ Highly linear PDM up to pulse width hard limit ◮ 9bit digital programmability per channel ◮ No crosstalk

  • bserved between

channels

experimental (vs simulated) results per channel Parameter Value Units Ibias bias<1:0>=00 0.97 (1) µA 01 1.9 (2) 10 4.6 (5) 11 9.1 (10) fc corner<1:0>=00 0.3 (0.25) Hz 01 3.9 (4.1) 10 50 (60) 11 625 (825) G gain<1:0>=00 27 (26) dB 01 34 (34) 10 40 (40) 11 46 (45) Gm transc<1:0>=00 (15) µS 01 (30) 10 (70) 11 (130) Cint cint<0>=0 (5) pF 1 (10) pF Total Harmonic Distortion <0.25 % Crosstalk <0.5 LSB Vnieq for Rsens=300kΩ (100) nVrms/ √ Hz Supply voltage 3.3 V Supply current 100 µA Silicon area 300×715 µm2

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 24

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 24/26

1 Introduction 2 ROIC Channel Architecture 3 Pre-Amplification and Filtering 4 Blind Cancellation and Lock-in Demodulation 5 Integrating A/D Conversion 6 Post Layout High Level Modeling 7 CMOS Integration and Experimental Results 8 Conclusions

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 25

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 25/26

Conclusions

◮ Digital read-out channel for IR spectroscopic gas recognition ◮ Fully integrable sub-Hz high-pass pre-amplification ◮ Blind cancellation and lock-in demodulation ◮ Highly linear integrating A/D conversion ◮ High-programmability (9bit) per channel ◮ Low-current (100µA) and compact (0.2mm2) channel

module in 0.35µm 2P4M CMOS technology

◮ Experimental results agree with simulated performance ◮ Post layout high level modeling ◮ No-crosstalk reported between channels

. . . thanks for your attention!

  • S. Sutula et al.

IMB-CNM(CSIC)

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SLIDE 26

DCIS 2010 Intro Channel Preamp Blind-Lock ADC Modeling Results Conclusions 26/26

Improvements?

◭ Pre-amplifier dynamic offset

¢Vsens Vtun1

M1

Vtun3

M3

¢Vout/Ut

1 2

  • 1
  • 2

4 8

  • 4
  • 8

¢Icap/Ituneff

M1 M3

¢Vout ¢Icap ¢Vsens Vtun1

M1

¢Vout/Ut

1 2

  • 1
  • 2

4 8

  • 4
  • 8

¢Icap/Ituneff ¢Vout ¢Icap (a) (b)

◭ OTA linear range

Imax

M3 M4 M9 M10

Iout

M11 M12 M6

Itun Imax

M2 M1 M7 M8 M5

Itun Vcom+ Vdiff 2 Vcom - Vdiff 2

◮ A 32-channel ROIC is under development!

  • S. Sutula et al.

IMB-CNM(CSIC)