DATABASE SYSTEM IMPLEMENTATION GT 4420/6422 // SPRING 2019 // - PowerPoint PPT Presentation

DATABASE SYSTEM IMPLEMENTATION GT 4420/6422 // SPRING 2019 // @JOY_ARULRAJ LECTURE #8: DATABASES ON NEW HARDWARE

2 ANATOMY OF A DATABASE SYSTEM Process Manager Connection Manager + Admission Control Query Parser Query Processor Query Optimizer Query Executor Query Lock Manager (Concurrency Control) Transactional Access Methods (or Indexes) Storage Manager Buffer Pool Manager Log Manager Shared Utilities Memory Manager + Disk Manager Networking Manager Source: Anatomy of a Database System

3 DATABASE HARDWARE People have been thinking about using hardware to accelerate DBMSs for decades. DA DATABA BASE MA MACHINES: AN IDE DEA WHOSE TIME ME HAS PASSED? D? A A CRITIQUE OF F THE FU FUTURE OF F DAT ATAB ABAS ASE MAC ACHINES University of Wisconsin 1983

4 DATABASE HARDWARE 1980s: Database Machines → Computational accelerators for efficient query processing → Embedded CPUs in active disks that push down query predicates to reduce the amount of data subsequently processed by the main CPU → Did not become mainstream because commodity hardware improved quickly thereby reducing the utility of custom hardware DA DATABA BASE MA MACHINES: AN IDE DEA WHOSE TIME ME HAS PASSED? D? A A CRITIQUE OF F THE FU FUTURE OF F DAT ATAB ABAS ASE MAC ACHINES University of Wisconsin 1983

5 DATABASE HARDWARE Source: A Domain- Specific Architecture for Deep Neural Networks

6 DATABASE HARDWARE 1980s: RISC microprocessors enjoyed 20 years of rapid performance gains till 2004 as they rode atop both: → Moore’s Law (2x more transistors at each new semiconductor process node) and → Dennard Scaling (2x faster at half the power consumption per transistor for each process node). Then Dennard Scaling died and individual processors stopped getting faster.

7 DATABASE HARDWARE 2000s: Industry compensated by relying solely on Moore’s Law. → Rapidly increasing the number of processors on one chip to usher in multicore era

8 DATABASE HARDWARE 2010s: The multicore era lasted for 10 years until Amdahl’s law kicked in. → There’s only so much exploitable parallelism in any given application → Few applications can keep dozens of processors busy. → Then Moore’s Law died.

9 AMDAHL’S LAW ! Execution time of task = S latency = % !"# $ &%''()% → P= fraction of task that can be parallelized ! → P = 0.9: S latency = < 10x ,.- *.! $ &%''()%

10 DATABASE HARDWARE → CPUs are not getting any faster. Constrained by the power wall (the chip’s overall temperature and power consumption) → High-density DRAM DIMMs have a higher potential for failure in manufacturing. Lower DIMM yields increase DRAM price. → Newer technologies: GPUs, NVM, InfiniBand DA DATABA BASE MA MACHINES: AN IDE DEA WHOSE TIME ME HAS PASSED? D? A A CRITIQUE OF F THE FU FUTURE OF F DAT ATAB ABAS ASE MAC ACHINES University of Wisconsin 1983

11 TODAY’S AGENDA Non-Volatile Memory GPU Acceleration

12 NON-VOLATILE MEMORY Emerging storage technology that provide low latency read/writes like DRAM, but with persistent writes and large capacities like SSDs. → aka Storage-class Memory, Persistent Memory First devices will be block-addressable (NVMe) Later devices will be byte-addressable.

13 FUNDAMENTAL ELEMENTS OF CIRCUITS

14 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor (ca. 1745)

15 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor (ca. 1745) (ca. 1827)

16 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor (ca. 1745) (ca. 1827) (ca. 1831)

17 FUNDAMENTAL ELEMENTS OF CIRCUITS In 1971, Leon Chua at Berkeley predicted the existence of a fourth fundamental element. A two-terminal device whose resistance depends on the voltage applied to it, but when that voltage is turned off it permanently remembers its last resistive state. TW TWO CENTU TURIES OF ME MEMR MRISTORS Nature Materials 2012

18 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor (ca. 1745) (ca. 1827) (ca. 1831)

19 FUNDAMENTAL ELEMENTS OF CIRCUITS Capacitor Resistor Inductor Memristor (ca. 1745) (ca. 1827) (ca. 1831) (ca. 1971)

20 MERISTORS In 2000s, a team at HP Labs led by Stanley Williams stumbled upon a nano-device that had weird properties that they could not understand. It wasn’t until they found Chua’s 1971 paper that they realized what they had invented. HO HOW WE FOUND THE HE MIS ISSIN ING ME MEMR MRISTOR IEEE Spectrum 2008

21 TECHNOLOGIES Phase-Change Memory (PRAM) Resistive RAM (ReRAM) Magnetoresistive RAM (MRAM)

22 PHASE-CHANGE MEMORY Storage cell is comprised of two metal electrodes separated by a resistive heater and the phase change material (chalcogenide). The value of the cell is changed based on Bitline how the material is heated. chalcogenide → A short pulse changes the cell to a ‘0’. → A long, gradual pulse changes the cell to a ‘1’. Heater Access PH PHASE CHANGE MEMORY ARCHITECTURE AN AND THE QUEST FO FOR SCAL ALAB ABILITY Communications of the ACM 2010

23 RESISTIVE RAM Two metal layers with two TiO 2 layers in between. Running a current one direction moves electrons from the top TiO 2 layer to the bottom, thereby changing the resistance. May be programmable storage fabric … Platinum → Blurring the gap between storage and compute TiO 2-x Layer → Bertrand Russell’s Material Implication Logic TiO 2 Layer Platinum HO HOW WE FOUND THE HE MIS ISSIN ING ME MEMR MRISTOR IEEE Spectrum 2008

24 MAGNETORESISTIVE RAM Stores data using magnetic storage elements instead of electric charge or current flows. Spin-Transfer Torque (STT-MRAM) is the leading technology for this type of NVM. → Supposedly able to scale to very small sizes (10nm) and have SRAM latencies. Fixed FM Layer → Oxide Layer Free FM Layer SP SPIN MEMORY SH SHOWS S ITS S MIGHT IEEE Spectrum 2014

25 WHY THIS IS FOR REAL THIS TIME Industry has agreed to standard technologies and form factors. Linux and Microsoft have added support for NVM in their kernels (DAX). Intel has added new instructions for flushing cache lines to NVM ( CLFLUSH , CLWB ).

26 NVM DIMM FORM FACTORS NVDIMM-F (2015) → Flash only. Has to be paired with DRAM DIMM. NVDIMM-N (2015) → Flash and DRAM together on the same DIMM. → Appears as volatile memory to the OS. NVDIMM-P (2018) → True persistent memory. No DRAM or flash.

27 NVM CONFIGURATIONS Source: Ismail Oukid

28 NVM CONFIGURATIONS DRAM as Hardware- Managed Cache DBMS DBMS Address Space Virtual Memory Subsystem DRAM NVM Source: Ismail Oukid

29 NVM CONFIGURATIONS DRAM as Hardware- Managed Cache DBMS DBMS Address Space Virtual Memory Subsystem DRAM NVM Source: Ismail Oukid

30 NVM CONFIGURATIONS DRAM as Hardware- NVM Next to Managed Cache DRAM DBMS DBMS DBMS Address Space DBMS Address Space Virtual Memory Subsystem Virtual Memory Subsystem DRAM DRAM NVM NVM Source: Ismail Oukid

31 NVM CONFIGURATIONS DRAM as Hardware- NVM Next to Managed Cache DRAM DBMS DBMS DBMS Address Space DBMS Address Space Virtual Memory Subsystem Virtual Memory Subsystem DRAM DRAM NVM NVM Source: Ismail Oukid

32 NVM CONFIGURATIONS DRAM as Hardware- NVM Next to NVM as Persistent Managed Cache DRAM Memory DBMS DBMS DBMS DBMS Address Space DBMS Address Space DBMS Address Space Virtual Memory Subsystem Virtual Memory Subsystem Buffer Pool DRAM NVM Disk DRAM NVM Filesystem Filesystem NVM Source: Ismail Oukid

33 NVM CONFIGURATIONS DRAM as Hardware- NVM Next to NVM as Persistent Managed Cache DRAM Memory DBMS DBMS DBMS DBMS Address Space DBMS Address Space DBMS Address Space Virtual Memory Subsystem Virtual Memory Subsystem Buffer Pool DRAM NVM Disk DRAM NVM Filesystem Filesystem NVM Source: Ismail Oukid

34 NVM FOR DATABASE SYSTEMS Block-addressable NVM is not that interesting. Byte-addressable NVM will be a game changer but will require some work to use correctly. → In-memory DBMSs will be better positioned to use byte- addressable NVM. → Disk-oriented DBMSs will initially treat NVM as just a faster SSD.

35 STORAGE & RECOVERY METHODS Understand how a DBMS will behave on a system that only has byte-addressable NVM. Develop NVM-optimized implementations of standard DBMS architectures. Based on the N-Store prototype DBMS. LE LET'S TALK LK ABOUT STORAGE & RECOVERY METHODS FO FOR R NO NON-VO VOLATILE MEMORY DATABASE SE SY SYST STEMS SIGMOD 2015

36 SYNCHRONIZATION Existing programming models assume that any write to memory is non-volatile. → CPU decides when to move data from caches to DRAM. The DBMS needs a way to ensure that data is flushed from caches to NVM.

37 SYNCHRONIZATION Existing programming models assume that any write to memory is non-volatile. → CPU decides when to move data from caches to DRAM. The DBMS needs a way to ensure that data is flushed from caches to NVM. Memory L1 Cache Controller L2 Cache

38 SYNCHRONIZATION Existing programming models assume that any write to memory is non-volatile. → CPU decides when to move data from caches to DRAM. The DBMS needs a way to ensure that data is flushed from caches to NVM. STORE Memory L1 Cache Controller L2 Cache