Data Hazards Consider the data dependencies in the following - PowerPoint PPT Presentation

6b.1 6b.2 Data Hazards • Consider the data dependencies in the following sequence SUB $2, $1, $3 – The last four are all dependent on EE 457 Unit 6b AND $12, $2, $5 register $2 OR $13, $6, $2 • But because of pipelining the ADD $14, $2, $2 instructions and, or, add could SW $15, 100($2) ____________ before the sub Data Hazards writes its new result • This is called a ___________ more specifically a RAW (_____ _____________) Hazard – If the RAW hazards is not handled, incorrect program execution may result 6b.3 6b.4 An Opening Example An Opening Example $2= old old old old old new new new new CC6 CC7 CC8 CC9 CC1 CC2 CC3 CC4 CC5 • The compiler’s solution is to insert nop (__________) New $2 avail. instructions SUB $2, $1, $3 IM DM Reg ALU Reg here • The effect is to push the dependency later in time AND $12, $2, $5 IM DM Reg ALU Reg IM DM Reg ALU Reg OR $13, $6, $2 SUB $2, $1, $3 SUB $2, $1, $3 DM IM ALU Reg Reg nop New $2 needed IM DM ADD $14, $2, $2 Reg ALU Reg nop (Why 3?) here nop IM ALU DM Reg Reg nop AND $12, $2, $5 OR $13, $6, $2 SW $15, 100($2) IM DM Reg ALU Reg IM DM Reg ALU Reg nop ADD $14, $2, $2 SW $15, 100($2) Do these instrucs. get the new value? IM DM nop Reg ALU Reg (Note: Usually a reg. is written at end of clock) AND $12, $2, $5 • Can the compiler solve this problem w/o hardware help? IM ALU DM Reg Reg …

6b.5 6b.6 Control for Data Hazards Stalling Strategy LW $t1,4($s0) • Two hardware solutions • Since we must be careful not to ADD $t5,$t1,$t4 read a ________ register value – __________________________ from the register file, we should – __________________________ Fetch Decode Exec. Mem. WB detect hazards in the ID stage • Stall Strategy: C1 LW and stall the instruction there! – Detect the hazard and stall the dependent instructions in the pipeline C2 ADD LW – If an instruction stalls, all until the _________________________ instructions behind it ________ C3 i ADD LW – Stalling is achieved by sending _____________ forward into the pipe – All instructions in front of it are C4 i ADD LW and not updating the stalled stage registers nop _________________________ C5 i ADD LW nop nop – Insert “bubbles” into the C6 i ADD nop nop nop _________________ (set all C7 i+1 i ADD nop nop control signals to 0 so no incorrect C8 i+2 i+1 i ADD nop behavior takes place) Using Stalls to Handle Dependencies (Data Hazards) 6b.7 6b.8 Detecting Data Hazards Hazard Detection Unit I/O • Only stall if a Write register in one of the last 3 stages matches one of the read registers in the ID stage • Need to stall if an instruction in the last 3 stages is going to WB.RegWrite PCWrite write a register the currently decoding instruction wants to read Hazard Mem.RegWrite IRWrite Detection EX.RegWrite EX/MEM Mem WB (i.e. R EAD- A FTER- W RITE) Unit Mem WB ID/EX MEM/WB ID.ReadRegA Stall • How would we know if an instruction in the pipe is going to ID.ReadRegB WB Con Ex trol write a register than an instruction in ID wants to read? IF/ID + Read Sh. – By comparing register ID values!! Reg. 1 # 5 Left 2 Pipeline Stage Register Pipeline Stage Register Read Pipeline Stage Register Instruction Register Reg. 2 # 5 Read 0 Addr. Write Zero data 1 PC Reg. # ALU Instruc. Res. Addr. Read Cases for Detecting Data Dependecies Write 0 data 2 I-Cache Data Read 1 1 1a. ID/EX._________ and ID/EX.WriteRegister == IF/ID.ReadRegister1 Data Register File 1b. ID/EX._________ and ID/EX.WriteRegister == IF/ID.ReadRegister2 Write Data 2a. EX/MEM._________ and EX/MEM.WriteRegister == IF/ID.ReadRegister1 Sign Extend 0 D-Cache 2b. EX/MEM._________ and EX/MEM.WriteRegister == IF/ID.ReadRegister2 16 32 1 3a. MEM/WB._________ and MEM/WB.WriteRegister == IF/ID.ReadRegister1 EX.WriteReg 3b. MEM/WB._________ and MEM/WB.WriteRegister == IF/ID.ReadRegister2 Mem.WriteReg WB.WriteReg

6b.9 6b.10 HDU Operation HDU Implementation • How long do we stall – If the hazard exists in the EX stage, we need to insert ___ bubbles Hazard Detection (wait ________) before restarting the pipeline EX Hazard ID/EX RegWrite and – If the hazard exists in the WB stage we only need to insert __ bubble ((ID/EX.WriteRegister = IF/ID.ReadRegister1) or (wait _____ cycle) (ID/EX.WriteRegister = IF/ID.ReadRegister2)) • So since the delay is time dependent does the HDU require a EX/MEM RegWrite and MEM Hazard ((EX/MEM.WriteRegister = IF/ID.ReadRegister1) or counter or state machine? (EX/MEM.WriteRegister = IF/ID.ReadRegister2)) – _____ The producer instruction will keep ____________ and eventually clear. The HDU works by simply checking if _____ hazard WB Hazard MEM/WB RegWrite and ((MEM/WB.WriteRegister = IF/ID.ReadRegister1) or exists in the forward stages and inserts a bubble into the ID/EX stage (MEM/WB.WriteRegister = IF/ID.ReadRegister2)) register – If an EX hazard exists it will take 3 cycles to clear and thus the HDU will detect an EX hazard in one clock, a MEM hazard in the next, and a WB hazard in the third inserting a bubble for each of these cycle = 3 bubbles 6b.11 6b.12 HDU Logic HDU Implementation • What if two hazards exist at the same time • Detection logic requires _______ __-bit – Again, any hazard should cause a bubble comparators along with some AND and OR – The producing instructions will continue to move forward and gates eventually clear Fetch Decode Exec. Mem. WB • Upon detection, HDU inserts a bubble into the C1 SUB ID/EX stage register SUB $2, $1, $3 C2 AND SUB AND $4, $2, $5 C3 OR AND SUB – Bubble = HW generated NOP = Turn all control OR $8, $2, $6 C4 signals to zeros ADD $9, $4, $2 C5 SLT $1, $6, $7 C6 C7 C8 C9

6b.13 6b.14 Key Idea While $2 is not written until WB stage, the subtraction result is available at the end of the ___ stage (beginning of the ____ stage) and can be _______________ to dependent instructions New $2 ____ ___________ SUB $2, $1, $3 IM DM ALU Reg Reg AND $12, $2, $5 IM DM ALU Reg Reg Register Forwarding/Bypassing IM DM ALU OR $13, $6, $2 Reg Reg REDUCING DATA HAZARDS IM DM ADD $14, $2, $2 ALU Reg Reg Register file can be designed such that the value being written can SW $15, 100($2) IM DM ALU Reg Reg immediately be forwarded to read ports 6b.15 6b.16 Forwarding Unit Register File Internal Forwarding • Internal Forwarding: rs Read + Sh. Reg. 1 # 5 Left 2 Pipeline Stage Register Pipeline Stage Register rt Read 0 Read – Value read = Value being written Instruction Register Pipeline Stage Register 1 Reg. 2 # data 1 5 0 2 Write Zero ALUSelA Reg. # ALU Read Reg #1 Read Reg #1 Res. Addr. Read Write 0 0 data 2 Read Data 1 $0 0 1 $0 0 1 Data 2 Register File $1 1 $1 1 Data Mem. or ALU result Write Read data 1 Read data 1 Data Write Sign Write 0 ALUSelB Read data 1 data ALUSrc data Extend D-Cache 16 32 Forwarding 1 0 Unit rs $31 31 $31 31 Prior ALU 1 rt Result rd Regwrite & Regwrite, WriteReg# WriteReg# 0 0 1 1 1 Read data 2 Mux Control Source Explanation Read data 2 0 ALUSelA & ALUSelB = 00 ID/EX The first (if ALUSelA) and/or second (ALUSelB) ALU input comes from the normal ID/EX stage Read data 2 register Register File Register File without with Internal The first (if ALUSelA) and/or second (ALUSelB) ALU input comes from the prior ALU result in Internal ALUSelA & ALUSelB = 01 EX/MEM 31 31 Forwarding the EX/MEM stage reg. Forwarding ALUSelA & ALUSelB = 10 MEM/WB The first (if ALUSelA) and/or second (ALUSelB) ALU input comes from the data memory or Read Reg #2 Read Reg #2 earlier ALU result

6b.17 6b.18 Forwarding Unit Addition Forwarding Unit vs. HDU • Since the HDU stalled instructions in the ID stage it • Remove the old HDU in the ID stage needed to compare 2 source ID’s with 3 destination • Add a new Forwarding Unit (FU) in the EX ID’s stage • Because we let instructions fetch stale register values – Like HDU it services dependent instructions and just replace them in the EX (or MEM) stage, the – Compares write register ID’s in later stages to read forwarding Unit compares 2 source ID’s with 2 register ID’s in earlier stages destination ID’s • HDU had 6 comparators while the FU requires 4 6b.19 6b.20 Hazards Hazard Definitions • EX Hazard • EX Hazard – HDU: Hazard occurs if data dependence between ID and If [ _____________________ EX stages and ( EX/MEM.WriteReg != 0 ) and ( ____________________________________) ] – FU: Between EX and MEM stage Then EX1 = True • MEM Hazard If ( EX1 = True ) then ALUSelA = ___ – HDU: Hazard occurs if data dependence between ID and MEM stages If [ ____________________ – FU: Between EX and WB stages and ( EX/MEM.WriteReg != 0 ) • Idea: Hazard is named based on who ________ the and ( ____________________________________) ] data the dependent instruction needs Then EX2 = True If ( EX2 = True ) then ALUSelB = ___