CS453 INTRODUCTION TO DATAFLOW ANALYSIS CS453 Lecture Register allocation using liveness analysis 1 Introduction to Data-flow analysis Last Time – Register allocation for expression trees and local and param vars Today – Register allocation in GCC and LLVM – Control flow graphs – 3-address code – Register allocation using liveness analysis Reading for this week – Ch 8 in online book These slides adapted from Calvin Lin and E. Christopher Lewis. CS453 Lecture Register allocation using liveness analysis 2
Introduction to Data-flow analysis r1 Previous lecture: r1 r2 – Register allocation for expression trees minimizing the register use. r1 r2 r2 r3 r1 r2 r3 r4 To generate better code (e.g. use fewer registers) we need to analyze our programs better – 3-address code – Control flow analysis and control flow graphs to determine dynamic characteristics of the program – Register allocation using liveness ( live : still needed) analysis CS453 Lecture Register allocation using liveness analysis 3 A Low-Level IR: 3-address code We want to do analysis on an Intermediate Representation: 3-address code – Linear representation: assignments, labels, (conditional) jumps – Typically language-independent and nearly corresponds to machine instructions, difference: no stack code, but (temporary) variables – There are named variables (parameters, variables) and temporaries (expressions). We can name the temporaries assuming unbounded number of (symbolic) registers. Example operations – (Indexed) copy x = y[i], y[i] = x, x = z, t1 = t2 – Unary / binary op x = op z, x = v op z, t1 = t2 op t3 – Address of p = & v – Dereference x = *p, * p = x – Pass param param t0 – Call t1 = call f, 1 – ( conditinal) Branch goto L1, if t1 goto L1 CS453 Lecture Intermediate Representations 4
Register Allocation in GCC and LLVM Comparison between GCC and LLVM – Both used in compiler research. GCC since 1987, LLVM since 2004. – LLVM has BSD-like license and GCC has GPL license. – Both have a 3-address code based IR (LLVM has LLVM, GCC has GIMPLE). – Both create a static single assignment representation for their 3-address code intermediate representation. GCC Register Allocation – Lower GIMPLE into RTL (Register transfer language) – Regional register allocator based on Chaitin-Briggs (coloring approach to register allocation that is based on concept of live ranges) LLVM Register Allocation – Fast (inside a single basic block), Basic, Greedy, PBQP – All but Fast based on live ranges Show http://arstechnica.com/apple/2009/08/mac-os-x-10-6/9/ and http://en.wikibooks.org/wiki/GNU_C_Compiler_Internals/GNU_C_Compiler_Architecture CS453 Lecture Register allocation using liveness analysis 5 Data-flow Analysis Idea – Data-flow analysis derives information about the dynamic behavior of a program by only examining the static code Example – How many registers do we need 1 a := 0 for the program on the right? 2 L1: b := a + 1 – Easy bound: the number of 3 c := c + b variables used + expr temp (4) 4 a := b * 2 – Better answer is found by considering the dynamic 5 if a < 9 goto L1 requirements of the program 6 return c CS453 Lecture Register allocation using liveness analysis 6
Liveness Analysis Definition – A variable is live at a particular point in the program if its value at that point will be used in the future ( dead , otherwise). ∴ To compute liveness at a given point, we need to look into the future Motivation: Register Allocation – A program contains an unbounded number of variables – Must execute on a machine with a bounded number of registers – Two variables can use the same register if they are never in use at the same time ( i.e, never simultaneously live). ∴ Register allocation uses liveness information CS453 Lecture Register allocation using liveness analysis 7 Control Flow Graphs (CFGs) Definition – A CFG is a graph whose nodes represent program statements and whose directed edges represent control flow 1 a = 0 Example 1 a := 0 2 b = a + 1 2 L1: b := a + 1 3 c := c + b 3 c = c + b 4 a := b * 2 4 a = b * 2 5 if a < 9 goto L1 return c 6 5 a<9 No Yes return c 6 CS453 Lecture Register allocation using liveness analysis 8
Terminology Flow Graph Terms – A CFG node has out-edges that lead to successor nodes and in-edges that come from predecessor nodes – pred[n] is the set of all predecessors of node n 1 a = 0 succ[n] is the set of all successors of node n 2 b = a + 1 Examples – Out-edges of node 5: (5 → 6) and (5 → 2) 3 c = c + b – succ[5] = {2,6} – pred[5] = {4} 4 a = b * 2 – pred[2] = {1,5} a<9 5 No Yes return c 6 CS453 Lecture Register allocation using liveness analysis 9 Liveness by Example What is the live range of b ? – Variable b is read in statement 4, 1 a = 0 so b is live on the (3 → 4) edge – Since statement 3 does not assign 2 b = a + 1 into b , b is also live on the (2 → 3) edge 3 c = c + b – Statement 2 assigns b , so any value of b on the (1 → 2) and 4 a = b * 2 (5 → 2) edges are not needed, so b is dead along these edges 5 a<9 No Yes b ’s live range is (2 → 3 → 4) return c 6 CS453 Lecture Register allocation using liveness analysis 10
Liveness by Example (cont) Live range of a – a is live from (1 → 2) and again from 1 a = 0 (4 → 5 → 2) – a is dead from (2 → 3 → 4) 2 b = a + 1 Live range of b 3 c = c + b – b is live from (2 → 3 → 4) 4 a = b * 2 Live range of c – c is live from 5 a<9 (entry → 1 → 2 → 3 → 4 → 5 → 2, 5 → 6) No Yes return c 6 Variables a and b are never simultaneously live, so they can share a register CS453 Lecture Register allocation using liveness analysis 11 Uses and Defs Def (or definition) a = 0 – An assignment of a value to a variable – def_node[v] = set of CFG nodes that define variable v – def[n] = set of variables that are defined at node n a < 9? Use – A read of a variable’s value v live – use_node[v] = set of CFG nodes that use variable v – use[n] = set of variables that are used at node n ∉ def_node[v] More precise definition of liveness ∈ use_node[v] – A variable v is live on a CFG edge if (1) ∃ a directed path from that edge to a use of v (node in use_node[v]), and (2) that path does not go through any def of v (no nodes in def_node[v]) CS453 Lecture Register allocation using liveness analysis 12
The Flow of Liveness Data-flow – Liveness of variables is a property that flows through the edges of the CFG a := 0 1 Direction of Flow 2 b := a + 1 – Liveness flows backwards through the CFG, because the behavior at future nodes 3 c := c + b determines liveness at a given node a := b * 2 4 – Consider a – Consider b 5 a < 9? – Other properties flow forward No Yes return c 6 CS453 Lecture Register allocation using liveness analysis 13 program points Liveness at Nodes edges We have liveness on edges just before computation a = 0 – How do we talk about just after computation liveness at nodes? Two More Definitions – A variable is live-out at a node if it is live on any of that node’s out-edges n live-out out-edges – A variable is live-in at a node if it is live on any of that node’s in-edges in-edges n live-in CS453 Lecture Register allocation using liveness analysis 14
Computing Liveness Rules for computing liveness (1) Generate liveness: live-in n use If a variable is in use[n], it is live-in at node n (2) Push liveness across edges: pred[n] live-out live-out live-out If a variable is live-in at a node n then it is live-out at all nodes in pred[n] n live-in (3) Push liveness across nodes: If a variable is live-out at node n and not in def[n] live-in n then the variable is also live-in at n live-out Data-flow equations (1) in[n] = use[n] ∪ (out[n] – def[n]) (3) out[n] = ∪ in[s] (2) s ∈ succ[n] CS453 Lecture Register allocation using liveness analysis 15 Solving the Data-flow Equations Algorithm for each node n in CFG initialize solutions in[n] = ∅ ; out[n] = ∅ repeat for each node n in CFG in’[n] = in[n] save current results out’[n] = out[n] in[n] = use[n] ∪ (out[n] – def[n]) solve data-flow equations out[n] = ∪ in[s] s ∈ succ[n] until in’[n]=in[n] and out’[n]=out[n] for all n test for convergence This is iterative data-flow analysis (for liveness analysis) CS453 Lecture Register allocation using liveness analysis 16
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