CS453 INTRODUCTION TO DATAFLOW ANALYSIS CS453 Lecture Register - - PDF document

CS453 INTRODUCTION TO DATAFLOW ANALYSIS

CS453 Lecture Register allocation using liveness analysis 1 CS453 Lecture Register allocation using liveness analysis 2

Introduction to Data-flow analysis

Last Time

– Register allocation for expression trees and local and param vars

Today

– Register allocation in GCC and LLVM – Control flow graphs – 3-address code – Register allocation using liveness analysis

Reading for this week

– Ch 8 in online book These slides adapted from Calvin Lin and E. Christopher Lewis.

CS453 Lecture Register allocation using liveness analysis 3

Introduction to Data-flow analysis

Previous lecture: – Register allocation for expression trees minimizing the register use. To generate better code (e.g. use fewer registers) we need to analyze our programs better – 3-address code – Control flow analysis and control flow graphs to determine dynamic characteristics of the program – Register allocation using liveness (live: still needed) analysis r1 r1 r2 r1 r2 r2 r3 r1 r2 r3 r4

CS453 Lecture Intermediate Representations 4

A Low-Level IR: 3-address code

We want to do analysis on an Intermediate Representation: 3-address code

– Linear representation: assignments, labels, (conditional) jumps – Typically language-independent and nearly corresponds to machine instructions, difference: no stack code, but (temporary) variables – There are named variables (parameters, variables) and temporaries (expressions). We can name the temporaries assuming unbounded number

• f (symbolic) registers.

Example operations

– (Indexed) copy x = y[i], y[i] = x, x = z, t1 = t2

– Unary / binary op x = op z, x = v op z, t1 = t2 op t3 – Address of

p = & v

– Dereference

x = *p, *p = x

– Pass param

param t0

– Call

t1 = call f, 1 – (conditinal) Branch goto L1, if t1 goto L1

Register Allocation in GCC and LLVM

Comparison between GCC and LLVM

– Both used in compiler research. GCC since 1987, LLVM since 2004. – LLVM has BSD-like license and GCC has GPL license. – Both have a 3-address code based IR (LLVM has LLVM, GCC has GIMPLE). – Both create a static single assignment representation for their 3-address code intermediate representation.

GCC Register Allocation

– Lower GIMPLE into RTL (Register transfer language) – Regional register allocator based on Chaitin-Briggs (coloring approach to register allocation that is based on concept of live ranges)

LLVM Register Allocation

– Fast (inside a single basic block), Basic, Greedy, PBQP – All but Fast based on live ranges

CS453 Lecture Register allocation using liveness analysis 5 Show http://arstechnica.com/apple/2009/08/mac-os-x-10-6/9/ and http://en.wikibooks.org/wiki/GNU_C_Compiler_Internals/GNU_C_Compiler_Architecture CS453 Lecture Register allocation using liveness analysis 6

Data-flow Analysis

Idea

– Data-flow analysis derives information about the dynamic behavior of a program by only examining the static code

a := 0

c := c + b

a := b * 2

if a < 9 goto L1

return c Example – How many registers do we need for the program on the right? – Easy bound: the number of variables used + expr temp (4) – Better answer is found by considering the dynamic requirements of the program

CS453 Lecture Register allocation using liveness analysis 7

Liveness Analysis

Definition

– A variable is live at a particular point in the program if its value at that point will be used in the future (dead, otherwise). ∴ To compute liveness at a given point, we need to look into the future

Motivation: Register Allocation

– A program contains an unbounded number of variables – Must execute on a machine with a bounded number of registers – Two variables can use the same register if they are never in use at the same time (i.e, never simultaneously live). ∴ Register allocation uses liveness information

CS453 Lecture Register allocation using liveness analysis 8

Control Flow Graphs (CFGs)

Definition

– A CFG is a graph whose nodes represent program statements and whose directed edges represent control flow

Example

a := 0

c := c + b

a := b * 2

if a < 9 goto L1

return c return c a = 0 b = a + 1 a<9

1 2 6 5 3 4 a = b * 2

c = c + b

Yes No

CS453 Lecture Register allocation using liveness analysis 9

Terminology

Flow Graph Terms

– A CFG node has out-edges that lead to successor nodes and in-edges that come from predecessor nodes – pred[n] is the set of all predecessors of node n succ[n] is the set of all successors of node n

Examples

– Out-edges of node 5: – succ[5] = – pred[5] = – pred[2] = return c a = 0 b = a + 1 a<9

1 2 6 5 3 4 a = b * 2

c = c + b (5→6) and (5→2) {2,6} {1,5} {4}

Yes No CS453 Lecture Register allocation using liveness analysis 10

Liveness by Example

What is the live range of b?

– Variable b is read in statement 4, so b is live on the (3 → 4) edge – Since statement 3 does not assign into b, b is also live on the (2→3) edge – Statement 2 assigns b, so any value of b on the (1→2) and (5→2) edges are not needed, so b is dead along these edges

b’s live range is (2→3→4)

return c a = 0 b = a + 1 a<9

1 2 6 5 3 4 a = b * 2

c = c + b

Yes No

CS453 Lecture Register allocation using liveness analysis 11

Liveness by Example (cont)

Live range of a

– a is live from (1→2) and again from (4→5→2) – a is dead from (2→3→4)

Live range of b

– b is live from (2→3→4)

Live range of c

– c is live from (entry→1→2→3→4→5→2, 5→6) return c a = 0 b = a + 1 a<9

1 2 6 5 3 4 a = b * 2

c = c + b

Yes No

Variables a and b are never simultaneously live, so they can share a register

CS453 Lecture Register allocation using liveness analysis 12

Uses and Defs

Def (or definition)

– An assignment of a value to a variable – def_node[v] = set of CFG nodes that define variable v – def[n] = set of variables that are defined at node n

Use

– A read of a variable’s value – use_node[v] = set of CFG nodes that use variable v – use[n] = set of variables that are used at node n

More precise definition of liveness

– A variable v is live on a CFG edge if

a = 0 a < 9? ∉ def_node[v] ∈ use_node[v] v live

(1) ∃ a directed path from that edge to a use of v (node in use_node[v]), and

(2) that path does not go through any def of v (no nodes in def_node[v])

CS453 Lecture Register allocation using liveness analysis 13

a := b * 2

5

c := c + b

The Flow of Liveness

Data-flow

– Liveness of variables is a property that flows through the edges of the CFG

Direction of Flow

– Liveness flows backwards through the CFG, because the behavior at future nodes determines liveness at a given node – Consider a – Consider b – Other properties flow forward a < 9? b := a + 1

Yes No 3 1

a := 0

4 6

return c

2 CS453 Lecture Register allocation using liveness analysis 14

Liveness at Nodes

edges a = 0

Two More Definitions

– A variable is live-out at a node if it is live on any of that node’s out-edges – A variable is live-in at a node if it is live on any of that node’s in-edges

We have liveness on edges

– How do we talk about liveness at nodes? just after computation just before computation

n live-out

• ut-edges

n live-in in-edges

program points

CS453 Lecture Register allocation using liveness analysis 15

Data-flow equations in[n] = use[n] ∪ (out[n] – def[n])

• ut[n] = ∪

in[s]

s ∈ succ[n]

(1) (3) (2)

Rules for computing liveness (1) Generate liveness:

If a variable is in use[n], it is live-in at node n

n live-in use live-in n live-out

(3) Push liveness across nodes:

If a variable is live-out at node n and not in def[n] then the variable is also live-in at n

live-out n live-in pred[n] live-out live-out

(2) Push liveness across edges:

If a variable is live-in at a node n then it is live-out at all nodes in pred[n]

Computing Liveness

CS453 Lecture Register allocation using liveness analysis 16

Solving the Data-flow Equations

Algorithm This is iterative data-flow analysis (for liveness analysis)

for each node n in CFG in[n] = ∅; out[n] = ∅ repeat for each node n in CFG in’[n] = in[n]

• ut’[n] = out[n]

in[n] = use[n] ∪ (out[n] – def[n])

• ut[n] = ∪ in[s]

until in’[n]=in[n] and out’[n]=out[n] for all n

s ∈ succ[n]

initialize solutions solve data-flow equations test for convergence save current results

CS453 Lecture Register allocation using liveness analysis 17

3 bc c 5 a 2 a b 1 a node # use def in out in out in out in out in out in out in out 4 b a 6 c 1st 2nd 3rd 4th 5th 6th 7th c a b a a bc a c a bc bc b b a a ac a c ac bc bc b b a ac ac ac c ac bc bc b b ac ac ac c ac c ac bc bc b bc ac ac ac c ac c ac bc bc bc bc ac ac ac c ac c ac bc bc bc bc ac ac ac

Data-flow Equations for Liveness in[n] = use[n] ∪ (out[n] – def[n])

• ut[n] = ∪ in[s]

s ∈ succ[n] Yes No 2 b := a + 1 3 c := c + b 1

a := 0

4 a := b * 2 5

a < 9?

6

return c

Example Liveness Analysis in the MeggyJava compiler

Currently …

– Parse into AST – Allocate space on stack for locals and parameters and space in heap for member variables – Use stack for expression evaluation – Generate AVR code from AST

To perform data-flow analysis …

– Need intermediate representation like 3-address code – Use temporaries/symbolic registers for expression results – Indicate uses and defs of temporaries and locals and parameters in each 3- address code instruction – Create a control-flow graph with each 3-address code instruction as a node

CS453 Lecture Register allocation using liveness analysis 18

CS453 Lecture Intermediate Representations 19

A Low-Level IR: 3-address code

3-address code

– Linear representation – Typically language-independent and nearly corresponds to machine instructions – Each var is assumed to have a base + offset – Assumes infinite temps (t#), or symbolic registers, are available

Example operations

– Copy x = z, t1 = t2 – Indexed copy x = y[i], y[i] = x, t1 = y[i] – Unary op x = op z – Binary op x = v op z, t1 = t2 op t3 – Address of p = & v – Load x = *p – Store *p = x, – Pass param param t0 – Call t1 = call f, 1 – Branch goto L1 – Cbranch if (x==y) goto L1

Expression Example

CS453 Lecture Register allocation using liveness analysis 20

Another MeggyJava Example

CS453 Lecture Register allocation using liveness analysis 21

int a; int b; int c; int d; int e; int [] v; int [] z; Foo r; a = b + c + (d+e); v[i] = z[i] * 3 + v.length; r.bar(42);

MeggyJava Loop Example

CS453 Lecture Register allocation using liveness analysis 22

int a; int b; a = 1; b = 0; while (a<7) { a = a + 1; b = b + 3; } Meggy.setPixel((byte)a, (byte) b, Meggy.BLUE);

CS453 Lecture Register allocation using liveness analysis 23

Register Allocation

Problem

– Assign an unbounded number of symbolic registers, or temporaries, to a fixed number of architectural registers – Simultaneously live data must be assigned to different architectural registers

Goal

– Minimize overhead of accessing data – Memory operations (loads & stores) – Register moves

CS453 Lecture Register allocation using liveness analysis 24

Scope of Register Allocation

Expression Local Loop Global Interprocedural

CS453 Lecture Register allocation using liveness analysis 25

Granularity of Allocation

What is allocated to registers?

– Variables – Live ranges/Webs (i.e., du-chains with common uses) – Values (i.e., definitions; same as variables with SSA)

s1: x := 5 s2: y := x s3: x := y+1 s4: ... x ... s5: x := 3 s6: ... x ...

Variables: 2 (x & y) Live Ranges/Web: 3 (s1→s2,s4; s2 → s3; s3,s5 → s6) Values: 4 (s1, s2, s3, s5, φ (s3,s5))

b1 b4 b2 b3

CS453 Lecture Register allocation using liveness analysis 26

t2 t1 t3 Global Register Allocation by Graph Coloring

Idea [Cocke 71], First allocator [Chaitin 81]

• 1. Construct interference graph G=(N,E)

– Represents notion of “simultaneously live” – Nodes are units of allocation (e.g., variables, live ranges, values) – ∃ edge (n1,n2) ∈ E if n1 and n2 are simultaneously live – Symmetric (not reflexive nor transitive)

• 2. Find k-coloring of G (for k registers)

– Adjacent nodes can’t have same color

• 3. Allocate the same register to all allocation units of the same color

– Adjacent nodes must be allocated to distinct registers

CS453 Lecture Register allocation using liveness analysis 27

Interference Graph Example (Variables)

a := ... b := ... c := ... ... a ... d := ... ... d ... a := ... ... c ... a := ... ... d ... ... d ... e := ... ... a ... ... e ... ... b ... c := ...

a d b c e

CS453 Lecture Register allocation using liveness analysis 28

Computing the Interference Graph

Use results of live variable analysis

for each symbolic-register/temporary/var ti do for each symbolic-register/temporary/var tj (j < i) do for each def ∈ {definitions of ti} do if (tj is live out at def) then E ← E ∪ (ti,tj)

Options

– treat all instructions the same – treat MOVE instructions special – which is better?

CS453 Lecture Register allocation using liveness analysis 29

Allocating Registers Using the Interference Graph

K-coloring

– Color graph nodes using up to k colors – Adjacent nodes must have different colors

Allocating to k registers ≡ finding a k-coloring of the interference graph

– Adjacent nodes must be allocated to distinct registers

• But. . .

– Optimal graph coloring is NP-complete – Optimal register allocation is NP-complete, too (must approximate) – What if we can’t k-color a graph? (must spill)

CS453 Lecture Register allocation using liveness analysis 30

Register Allocation: Spilling

If we can’t find a k-coloring of the interference graph

– Spill variables (nodes) until the graph is colorable

Choosing variables to spill

– Choose arbitrarily or – Choose least frequently accessed variables – Break ties by choosing nodes with the most conflicts in the interference graph – Yes, these are heuristics!

CS453 Lecture Register allocation using liveness analysis 31

a d b c f e Spilling (Original CFG and Interference Graph)

a := ... b := ... c := ... ... a ... d := ... ... c ... f := ... ... d ... ... d ... e := ... ... f ... ... e ... ... b ... c := ... ... d ... f := ...

CS453 Lecture Register allocation using liveness analysis 32

a d b c f e Spilling (After spilling b )

a := ... b := ... *(Y+4) := b c := ... ... a ... d := ... ... c ... f := ... ... d ... ... d ... e := ... ... f ... ... e ... b = *(Y+4) ... b ... c := ... ... d ... f := ...

CS453 Lecture Register allocation using liveness analysis 33

Simple Greedy Algorithm for Register Allocation

for each n ∈ N do { select n in decreasing order of weight } if n can be colored then do it { reserve a register for n } else Remove n (and its edges) from graph { allocate n to stack (spill) }

a d c f e

a := ... r24 := ... *(Y+4):= r24 c := ... ... a ... d := ... ... d ... e := ... ... f ... ... e ... r24 = *(Y+4) ... r24 ...

(After spilling b )

CS453 Lecture Register allocation using liveness analysis 34

Weighted order: a b c d f e

Example a d b c f e

Attempt to 3-color this graph ( , , )

What if you use a different order?

CS453 Lecture Register allocation using liveness analysis 35

a b Example

Weighted order: a b c

Attempt to 2-color this graph ( , )

c

CS453 Lecture Register allocation using liveness analysis 36

Concepts

Liveness

– Used in register allocation – Generating liveness – Flow and direction – Data-flow equations and analysis

3-address code and Control flow graphs Register allocation

– scope of allocation – granularity: what is being allocated to a register – order that allocation units are visited in matters in all heuristic algorithms

Global approach: greedy coloring

CS453 Lecture Register allocation using liveness analysis 37

Liveness in the MiniJava compiler