CPSC 121: Models of Computation Instructor: Bob Woodham - - PowerPoint PPT Presentation

CPSC 121: Models of Computation

Instructor: Bob Woodham woodham@cs.ubc.ca

Department of Computer Science University of British Columbia

Lecture Notes 2008/2009, Section 203

CPSC 121: Models of Computation

Menu January 26, 2009

Topics: Multiplexer (MUX) Other Combinational Circuits: — Adders and Decoders Reading: Today: Lab 3 (when available) Next: Epp 2.3, 2.2, 2.4 Reminders: Assignment 1 due Friday, January 30, 17:00 In-class Quiz 1 Wednesday, February 4 Midterm exam Tuesday, February 24 (evening) READ the WebCT Vista course announcements board

CPSC 121: Models of Computation

Multiplexer (MUX)

Consider the following “black box” circuit specificaton:

input a input b input c

• utput y

If c is "1" then copy b to y Otherwise, copy a to y

Input c plays the role of a control whose value determines whether we select a or b as output

CPSC 121: Models of Computation

Truth Table MUX

c b a y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CPSC 121: Models of Computation

Truth Table MUX

c b a y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If c is 1, copy b to output y.

CPSC 121: Models of Computation

Truth Table MUX

c b a y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If c is 1, copy b to output y. Otherwise, c is 0 and we copy a to

• utput y

CPSC 121: Models of Computation

Truth Table MUX

c b a y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 If c is 1, copy b to output y. Otherwise, c is 0 and we copy a to

• utput y

CPSC 121: Models of Computation

Multiplexer (MUX)

Here’s one gate symbol used to represent the MUX we have defined:

1

Y A B C

Recall: Input C plays the role of a control whose value determines whether we select A or B as output

CPSC 121: Models of Computation

Multiplexer Implementation

Task: Determine a circuit that implements a (2 input) MUX Let’s use a Sum–of–Products (SOP) representation

1

Y A B C

C B A y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Recall: Input C plays the role of a control whose value determines whether we select A or B as output

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α, we have the following simplification rule (i.e., logical equivalence): αA + αA ≡ α Thus, we determine Y ≡ CBA + CBA + CBA + CBA ≡ CA + CBA + CBA ≡ CA + CB

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α, we have the following simplification rule (i.e., logical equivalence): αA + αA ≡ α Thus, we determine Y ≡ CBA + CBA + CBA + CBA ≡ CA + CBA + CBA ≡ CA + CB

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α, we have the following simplification rule (i.e., logical equivalence): αA + αA ≡ α Thus, we determine Y ≡ CBA + CBA + CBA + CBA ≡ CA + CBA + CBA ≡ CA + CB

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α, we have the following simplification rule (i.e., logical equivalence): αA + αA ≡ α Thus, we determine Y ≡ CBA + CBA + CBA + CBA ≡ CA + CBA + CBA ≡ CA + CB

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

Here’s the corresponding circuit

Y A C B

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

Let’s look at timing. . .

Y A C B

Y C B A

1 1 1 1

There is a (short) “glitch” (aka “hazard”) in the output Y NOTE: This glitch is a transient effect. The steady state behaviour of our circuit is fine

CPSC 121: Models of Computation

Multiplexer Implementation (cont’d)

Here’s a safe (aka lenient) design corresponding to Y ≡ CA + CB + AB

Y A C B

NOTE: We have added an extra AND gate. It is redundant (with respect to the steady state behaviour) of our MUX. But, it eliminates the “glitch” from our previous implementation

CPSC 121: Models of Computation

4-Input Multiplexer as a Tree

Consider the circuit

1 1 1

S0 S1 I0 I1 I2 I3 Y

It implements the truth table S1 S0 Y I0 1 I1 1 I2 1 1 I3

CPSC 121: Models of Computation

4-Bit Adder

Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b

4−bit adder c s0 s1 s2 s3 b0 b1 b2 b3 a0 a1 a2 a3

• ut

c

in

We’ll need (and the figure shows) two more wires: 1 additional input, cin, and 1 additional output, cout

CPSC 121: Models of Computation

Half-Adder

Let’s design a component circuit to add two 1-bit values Define a 1-bit half-adder, s = a + b, by truth table a b s c 1 1 1 1 1 1 1 Observe: s ≡ a ⊕ b c ≡ a ∧ b

CPSC 121: Models of Computation

Half-Adder (cont’d)

b a c s

CPSC 121: Models of Computation

Another Half-Adder

s c b a

NOTE: The only gates used here are: NOT, AND and OR

CPSC 121: Models of Computation

1-Bit Full Adder

Define a 1-bit full-adder, s = a + b, by truth table a b cin s cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Again, let’s try to define s and cout as propositions involving the 3 inputs a, b and cin

CPSC 121: Models of Computation

1-Bit Full Adder (cont’d)

For s: Observe s = 1 when the number of 1s among a, b, cin is odd s ≡ a ⊕ b ⊕ cin For cout: cout ≡ (a ∧ b) ∨ ((a ⊕ b) ∧ cin)

CPSC 121: Models of Computation

1-Bit Full Adder (cont’d)

cout s cin a b

CPSC 121: Models of Computation

1-Bit Full Adder

FA cin a b s cout

CPSC 121: Models of Computation

4-Bit Adder (cont’d)

FA FA FA FA b0 b1 b2 b3 a0 a1 a2 a3 s0 s1 s2 s3 cout

CPSC 121: Models of Computation

4-Bit Adder

Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b

4−bit adder c s0 s1 s2 s3 b0 b1 b2 b3 a0 a1 a2 a3

• ut

c

in

We’ll need (and the figure shows) two more wires: 1 additional input, cin, and 1 additional output, cout

CPSC 121: Models of Computation

4-Bit Subtractor

s0 s1 s2 s3 cout FA FA FA FA 1 b0 a0 b1 a1 b2 a2 b3 a3

CPSC 121: Models of Computation

Detecting Overflow in n-Bit Binary Addition

Case 1: Adding 2 unsigned integers Check if the last carry, cn−1, is one Case 2: Adding 2 signed integers A simple check of last carry, cn−1, doesn’t work RECALL: Ignoring carry is key to 2’s complement

CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition

Let s = a + b Note 1: It’s not possible to produce overflow when adding integers of opposite sign (i.e., when the MSBs of a and b differ). The result, s, is either less positive than the most positive of a and b or less negative than the most negative of a and b (i.e., it’s closer to zero) Note 2: There are two kind’s of overflow:

1

The result is too positive (i.e., a > 0, b > 0, s < 0). In this case, the MSBs are, respectively, an−1 = bn−1 = 0; sn−1 = 1

2

The result is too negative (i.e., a < 0, b < 0, s > 0). In this case, the MSBs are, respectively, an−1 = bn−1 = 1; sn−1 = 0

CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition (cont’d)

We can put this into a truth table: an−1 bn−1 sn−1 Overflow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 By inspection of the truth table, we see we get overflow if and

• nly if an−1 = bn−1 and bn−1 = sn−1. Thus, a proposition for
• verflow is

(an−1 ↔ bn−1) ∧ (bn−1 ⊕ sn−1)

CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition (cont’d)

We can implement this as a circuit:

• verflow

sn−1 bn−1 an−1

CPSC 121: Models of Computation

Decoder

A decoder is a circuit that accepts an n-bit binary code (aka an address) and converts it into (up to) 2n unique outputs. That is, exactly one of the 2n outputs is set to 1 and all the rest are set to 0.

CPSC 121: Models of Computation

A Simple Decoder Example

Suppose our Central Processing Unit (CPU) accepts instructions in which 2 bits encode which one of 4 arithmetic

• perations to perform (add, sub, mult, div)

Our decoder must accept the 2-bit code as input and set the appropriate output to 1 Once again, we proceed via a truth table

CPSC 121: Models of Computation

A Simple Decoder Example

Let the 2-bit code be xy codes

• utputs

x y add sub mult div 1 1 1 1 1 1 1 1

CPSC 121: Models of Computation

A Simple Decoder Example

Let the 2-bit code be xy codes

• utputs

x y add sub mult div 1 1 1 1 1 1 1 1 With 2-bits, there are 4 codes.

CPSC 121: Models of Computation

A Simple Decoder Example

Let the 2-bit code be xy codes

• utputs

x y add sub mult div 1 1 1 1 1 1 1 1 With 2-bits, there are 4 codes. Fill the diagonal with 1s, 0 the remaining entries

CPSC 121: Models of Computation

A Simple Decoder Example

Let the 2-bit code be xy codes

• utputs

x y add sub mult div 1 1 1 1 1 1 1 1 With 2-bits, there are 4 codes. Fill the diagonal with 1s, 0 the remaining entries NOTE: We are designing this decoder. The codes are not predefined for us

CPSC 121: Models of Computation

A Simple Decoder Example (cont’d)

We have the following four propositions: add ≡ x ∧ y sub ≡ x ∧ y mult ≡ x ∧ y div ≡ x ∧ y and the circuit:

add sub mult div x y

CPSC 121: Models of Computation

Example: Arithmetic Overflow Re-Visited

Quick Review: So far, we’ve dealt with 3 cases:

1

Unsigned addition. (Check cout)

2

Signed addition. (Circuit based on an−1, bn−1, sn−1)

3

Signed subtraction. (Circuit based on an−1, bn−1, sn−1) But, there’s a 4th case:

4

Negation Recall, for n-bit signed integers, the numbers represented range from −2n−1 to 2n−1 − 1 The negation of −2n−1 can not be represented Again, we get overflow

CPSC 121: Models of Computation

Example: Arithmetic Overflow Re-Visited

A circuit to check for this case of overflow is quite simple. We detect the case b = −2n−1 = 1000 . . . 02 explicitly

• verflow

b0 b1 b2 bn−2 bn−1

CPSC 121: Models of Computation

Example: Arithmetic Overflow Re-Visited

In order to choose between the 4 overflow conditions, we design a 2-bit code, c1c0, as follows: c1 c0

• peration

unsigned addition 1 signed addition 1 signed subtraction 1 1 negate b Think of these 2 bits as “control bits”

CPSC 121: Models of Computation

Example: Arithmetic Overflow Re-Visited

Now, here’s the circuit:

CPSC 121: Models of Computation

More Gate Tricks

Let a1, a2, . . . ,an be n Boolean variables a1 ⊕ a2 ⊕ . . . ⊕ an = 1 if and only if the number of 1s in the n-bit binary number a1a2 . . . an is odd Note 1: If the number of 1s is odd then the number is said to have odd parity Note 2: Determining a propositional formula for odd parity based on truth tables and Sum–of–Products (SOP) methods is quite difficult/tedious (when n is large) Note 3: Suppose only 2-input XOR gates are available. We can implement n-input XOR either as a “chain” or as a “tree” of 2-input XOR gates

CPSC 121: Models of Computation

8-Input MUX for Full-Adder cout

Consider the truth table and 8-input MUX a b cin cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 2 3 4 5 6 7 cout a, b, c 1 1 1 1

in CPSC 121: Models of Computation

MUX Designs: Now and in the Future

MUXes are used to build truth table lookup implementations of combinational circuits There are technologies that make the creation of very large lookup tables quite feasible (and effective when combined with MUX-based design) Examples include:

1

Read Only Memory (ROM), (one-time) Programmable ROMS (PROMS), Erasable Programmable ROMS (EPROMS), etc.

2

Programmable Logic Arrays (PLAs)

3

Gate Array Devices

4

Standard Cells

CPSC 121: Models of Computation

Combinational Circuits: Summary

A circuit element is a combinational device if:

1

it has one or more digital inputs

2

it has one or more digital outputs

3

there is a functional specification that gives the value of each output for every possible combination of valid input values

4

there is a timing specification that gives an upper bound on the required time for the device to compute the specified

• utput values from an arbitrary set of stable, valid input

values

CPSC 121: Models of Computation

Combinational Circuits: Summary

A set of interconnected elements is a combinational device if:

1

each circuit element is a combinational device

2

every input is connected to exactly one output or to some vast supply of 0s and 1s

3

the circuit contains no directed cycles

CPSC 121: Models of Computation

Combinational Circuits: Summary

Combinational devices are:

1

discrete

2

memoryless (valid outputs always reflect current inputs)

3

noise free

CPSC 121: Models of Computation