CPSC 121: Models of Computation Instructor: Bob Woodham - PowerPoint PPT Presentation

CPSC 121: Models of Computation Instructor: Bob Woodham woodham@cs.ubc.ca Department of Computer Science University of British Columbia Lecture Notes 2008/2009, Section 203 CPSC 121: Models of Computation

Menu January 26, 2009 Topics: Multiplexer (MUX) Other Combinational Circuits: — Adders and Decoders Reading: Today: Lab 3 (when available) Next: Epp 2.3, 2.2, 2.4 Reminders: Assignment 1 due Friday, January 30, 17:00 In-class Quiz 1 Wednesday, February 4 Midterm exam Tuesday, February 24 (evening) READ the WebCT Vista course announcements board CPSC 121: Models of Computation

Multiplexer (MUX) Consider the following “black box” circuit specificaton: input a If c is "1" then copy b to y input b Otherwise, copy a to y output y input c Input c plays the role of a control whose value determines whether we select a or b as output CPSC 121: Models of Computation

Truth Table MUX c b a y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 CPSC 121: Models of Computation

Truth Table MUX c b a y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 If c is 1, copy b to output y. CPSC 121: Models of Computation

Truth Table MUX c b a y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 If c is 1, copy b to output y. Otherwise, c is 0 and we copy a to output y CPSC 121: Models of Computation

Truth Table MUX c b a y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 If c is 1, copy b to output y. Otherwise, c is 0 and we copy a to output y CPSC 121: Models of Computation

Multiplexer (MUX) Here’s one gate symbol used to represent the MUX we have defined: 0 A Y B 1 C Recall: Input C plays the role of a control whose value determines whether we select A or B as output CPSC 121: Models of Computation

Multiplexer Implementation Task: Determine a circuit that implements a (2 input) MUX Let’s use a Sum–of–Products (SOP) representation C B A y 0 0 0 0 0 A 0 0 1 1 Y 0 1 0 0 0 1 1 1 B 1 1 0 0 0 1 0 1 0 C 1 1 0 1 1 1 1 1 Recall: Input C plays the role of a control whose value determines whether we select A or B as output CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α , we have the following simplification rule (i.e., logical equivalence): α A + α A ≡ α Thus, we determine Y CBA + CBA + CBA + CBA ≡ ≡ CA + CBA + CBA ≡ CA + CB CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α , we have the following simplification rule (i.e., logical equivalence): α A + α A ≡ α Thus, we determine Y CBA + CBA + CBA + CBA ≡ ≡ CA + CBA + CBA ≡ CA + CB CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α , we have the following simplification rule (i.e., logical equivalence): α A + α A ≡ α Thus, we determine Y CBA + CBA + CBA + CBA ≡ ≡ CA + CBA + CBA ≡ CA + CB CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) The standard SOP representation of our truth table is: Y ≡ CBA + CBA + CBA + CBA For any proposition α , we have the following simplification rule (i.e., logical equivalence): α A + α A ≡ α Thus, we determine Y CBA + CBA + CBA + CBA ≡ ≡ CA + CBA + CBA ≡ CA + CB CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) Here’s the corresponding circuit A C Y B CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) Let’s look at timing. . . A C Y B 1 A 0 1 B 0 1 C 0 1 Y 0 There is a (short) “glitch” (aka “hazard”) in the output Y NOTE: This glitch is a transient effect. The steady state behaviour of our circuit is fine CPSC 121: Models of Computation

Multiplexer Implementation (cont’d) Here’s a safe (aka lenient) design corresponding to Y ≡ CA + CB + AB A C Y B NOTE: We have added an extra AND gate. It is redundant (with respect to the steady state behaviour) of our MUX. But, it eliminates the “glitch” from our previous implementation CPSC 121: Models of Computation

4-Input Multiplexer as a Tree Consider the circuit 0 I 0 I 1 1 0 Y 1 0 I 2 I 3 1 S 0 S 1 It implements the truth table S 1 S 0 Y 0 0 I 0 0 1 I 1 1 0 I 2 1 1 I 3 CPSC 121: Models of Computation

4-Bit Adder Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 c in 4−bit adder c out s 3 s 2 s 1 s 0 We’ll need (and the figure shows) two more wires: 1 additional input, c in , and 1 additional output, c out CPSC 121: Models of Computation

Half-Adder Let’s design a component circuit to add two 1-bit values Define a 1-bit half-adder, s = a + b , by truth table a b s c 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Observe: s ≡ a ⊕ b c ≡ a ∧ b CPSC 121: Models of Computation

Half-Adder (cont’d) a s c b CPSC 121: Models of Computation

Another Half-Adder a s b c NOTE: The only gates used here are: NOT, AND and OR CPSC 121: Models of Computation

1-Bit Full Adder Define a 1-bit full-adder, s = a + b , by truth table a b c in s c out 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Again, let’s try to define s and c out as propositions involving the 3 inputs a, b and c in CPSC 121: Models of Computation

1-Bit Full Adder (cont’d) For s : Observe s = 1 when the number of 1s among a, b, c in is odd s ≡ a ⊕ b ⊕ c in For c out : c out ≡ ( a ∧ b ) ∨ (( a ⊕ b ) ∧ c in ) CPSC 121: Models of Computation

1-Bit Full Adder (cont’d) a s c in b c out CPSC 121: Models of Computation

1-Bit Full Adder a b c in FA c out s CPSC 121: Models of Computation

4-Bit Adder (cont’d) a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 0 FA FA FA FA c out s 3 s 2 s 1 s 0 CPSC 121: Models of Computation

4-Bit Adder Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 c in 4−bit adder c out s 3 s 2 s 1 s 0 We’ll need (and the figure shows) two more wires: 1 additional input, c in , and 1 additional output, c out CPSC 121: Models of Computation

4-Bit Subtractor a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 1 FA FA FA FA c out s 3 s 2 s 1 s 0 CPSC 121: Models of Computation

Detecting Overflow in n-Bit Binary Addition Case 1: Adding 2 unsigned integers Check if the last carry, c n − 1 , is one Case 2: Adding 2 signed integers A simple check of last carry, c n − 1 , doesn’t work RECALL: Ignoring carry is key to 2’s complement CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition Let s = a + b Note 1: It’s not possible to produce overflow when adding integers of opposite sign (i.e., when the MSBs of a and b differ). The result, s , is either less positive than the most positive of a and b or less negative than the most negative of a and b (i.e., it’s closer to zero) Note 2: There are two kind’s of overflow: The result is too positive (i.e., a > 0 , b > 0 , s < 0). In this 1 case, the MSBs are, respectively, a n − 1 = b n − 1 = 0 ; s n − 1 = 1 The result is too negative (i.e., a < 0 , b < 0 , s > 0). In this 2 case, the MSBs are, respectively, a n − 1 = b n − 1 = 1 ; s n − 1 = 0 CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition (cont’d) We can put this into a truth table: a n − 1 b n − 1 s n − 1 Overflow 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 By inspection of the truth table, we see we get overflow if and only if a n − 1 = b n − 1 and b n − 1 � = s n − 1 . Thus, a proposition for overflow is ( a n − 1 ↔ b n − 1 ) ∧ ( b n − 1 ⊕ s n − 1 ) CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition (cont’d) We can implement this as a circuit: a n−1 b n−1 overflow s n−1 CPSC 121: Models of Computation

Decoder A decoder is a circuit that accepts an n-bit binary code (aka an address ) and converts it into (up to) 2 n unique outputs. That is, exactly one of the 2 n outputs is set to 1 and all the rest are set to 0. CPSC 121: Models of Computation

A Simple Decoder Example Suppose our Central Processing Unit (CPU) accepts instructions in which 2 bits encode which one of 4 arithmetic operations to perform ( add, sub, mult, div ) Our decoder must accept the 2-bit code as input and set the appropriate output to 1 Once again, we proceed via a truth table CPSC 121: Models of Computation

A Simple Decoder Example Let the 2-bit code be xy codes outputs x y add sub mult div 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 CPSC 121: Models of Computation