Covert and Side Channel Attacks and Defenses Mengjia Yan Fall 2020 - - PowerPoint PPT Presentation

▶
covert and side channel attacks and defenses
SMART_READER_LITE
LIVE PREVIEW

Covert and Side Channel Attacks and Defenses Mengjia Yan Fall 2020 - - PowerPoint PPT Presentation

Nov 28, 2023 356 likes •1.03k views

Covert and Side Channel Attacks and Defenses Mengjia Yan Fall 2020 Based on slides from Christopher W. Fletcher Reminder Lab assignment will be released 09/21 Monday Recommend to read Cache missing for fun and profit. (2005).

slide-1
SLIDE 1

Covert and Side Channel Attacks and Defenses

Mengjia Yan Fall 2020 Based on slides from Christopher W. Fletcher

slide-2
SLIDE 2

Reminder

  • Lab assignment will be released 09/21 Monday
  • Recommend to read ”Cache missing for fun and profit.” (2005).
  • Check out the presentation schedule on course website
  • 7 slots empty, volunteer or invited speaker or Mengjia/Miles

6.888 L4-Covert and Side Channels 2

slide-3
SLIDE 3

Resources

  • Side channel tutorial website
  • https://sites.google.com/view/arch-sec/home
  • External resources
  • Mastik, a toolkit for uarch side channels: https://cs.adelaide.edu.au/~yval/Mastik/
  • Survey on microarchitectural timing attacks: https://eprint.iacr.org/2016/613.pdf
  • Survey on transient execution attacks: https://arxiv.org/abs/1811.05441

6.888 L4-Covert and Side Channels 3

slide-4
SLIDE 4

What is Covert and Side Channel?

Covert channel:

  • Intended communication between two or more security parties

Side channel:

  • Unintended communication between two or more security parties

6.888 L4-Covert and Side Channels 4

slide-5
SLIDE 5

What is Covert and Side Channel?

Covert channel:

  • Intended communication between two or more security parties

Side channel:

  • Unintended communication between two or more security parties

In both cases:

  • Communication should not be possible, following system semantics
  • The communication medium is not designed to be a communication channel

6.888 L4-Covert and Side Channels 4

slide-6
SLIDE 6

What is Covert and Side Channel?

Covert channel:

  • Intended communication between two or more security parties

Side channel:

  • Unintended communication between two or more security parties

In both cases:

  • Communication should not be possible, following system semantics
  • The communication medium is not designed to be a communication channel

Covert channel can show “best case” leakage

6.888 L4-Covert and Side Channels 4

slide-7
SLIDE 7

Scope

CIA: Confidentiality, Integrity, Availability

6.888 L4-Covert and Side Channels 5

slide-8
SLIDE 8

Scope

CIA: Confidentiality, Integrity, Availability

Confidentiality: was data being computed upon not revealed to an un-permitted party? Integrity: was the computation performed correctly, returning the correct result? Availability: did the computational resource carry out the task at all?

6.888 L4-Covert and Side Channels 5

slide-9
SLIDE 9

Scope

CIA: Confidentiality, Integrity, Availability

Confidentiality: was data being computed upon not revealed to an un-permitted party? Integrity: was the computation performed correctly, returning the correct result? Availability: did the computational resource carry out the task at all?

Confidentiality/Privacy

6.888 L4-Covert and Side Channels 5

slide-10
SLIDE 10

Scope

CIA: Confidentiality, Integrity, Availability

Confidentiality: was data being computed upon not revealed to an un-permitted party? Integrity: was the computation performed correctly, returning the correct result? Availability: did the computational resource carry out the task at all?

Confidentiality/Privacy Side/covert channels

6.888 L4-Covert and Side Channels 5

slide-11
SLIDE 11

Scope

CIA: Confidentiality, Integrity, Availability

Confidentiality: was data being computed upon not revealed to an un-permitted party? Integrity: was the computation performed correctly, returning the correct result? Availability: did the computational resource carry out the task at all?

Confidentiality/Privacy Side/covert channels Microarchitectural channels

6.888 L4-Covert and Side Channels 5

slide-12
SLIDE 12

Side Channels Are Almost Everywhere

slide-13
SLIDE 13

Daily Life Examples

  • Acoustic side channels
  • Monitor keystrokes
  • You only need: a cheap microphone + an ML model

6.888 L4-Covert and Side Channels 7

slide-14
SLIDE 14

Daily Life Examples

  • Acoustic side channels
  • Monitor keystrokes
  • You only need: a cheap microphone + an ML model
  • Network traffic contention side channel
  • If you want to be an active attacker, try stress test

6.888 L4-Covert and Side Channels 7

slide-15
SLIDE 15

“Hear” The Screen

Genkin et. al. Synesthesia: Detecting Screen Content via Remote Acoustic Side Channels. S&P’19

frequency time

Sound Spectogram

6.888 L4-Covert and Side Channels 8

slide-16
SLIDE 16

“Hear” The Screen

(A) is the LCD panel, (B) is the screen’s digital logic and image rendering board and, (C) is the screen’s power supply board.

6.888 L4-Covert and Side Channels 9

slide-17
SLIDE 17

Network Side Channels

  • Website Fingerprinting

Lescisin et. al. Tools for Active and Passive Network Side-Channel Detection for Web Applications. WOOT’18 Cai et. al. Touching from a distance: Website fingerprinting attacks and defenses. CCS’12.

6.888 L4-Covert and Side Channels 10

slide-18
SLIDE 18

Network Side Channels

  • Website Fingerprinting
  • Response dependent:
  • iSideWith.com
  • Real-time feedback:
  • Google Search auto-complete

Lescisin et. al. Tools for Active and Passive Network Side-Channel Detection for Web Applications. WOOT’18 Cai et. al. Touching from a distance: Website fingerprinting attacks and defenses. CCS’12.

6.888 L4-Covert and Side Channels 10

slide-19
SLIDE 19

Physical v.s. Timing v.s. uArch Channel

  • What can the adversary observe?

6.888 L4-Covert and Side Channels 11

slide-20
SLIDE 20

Physical v.s. Timing v.s. uArch Channel

  • What can the adversary observe?

Processor Power, EM, sound, etc. Attacker requires measurement equipment à physical access Physical channels Victim

6.888 L4-Covert and Side Channels 11

slide-21
SLIDE 21

Physical v.s. Timing v.s. uArch Channel

  • What can the adversary observe?

Processor Power, EM, sound, etc. Attacker requires measurement equipment à physical access Processor Response time Attacker may be remote (e.g.,

  • ver an internet connection)

Physical channels Timing channels Victim Victim

6.888 L4-Covert and Side Channels 11

slide-22
SLIDE 22

Physical v.s. Timing v.s. uArch Channel

  • What can the adversary observe?

Processor Power, EM, sound, etc. Attacker requires measurement equipment à physical access Processor Response time Attacker may be remote (e.g.,

  • ver an internet connection)

Physical channels Timing channels Processor Attacker may be remote,

  • r be co-located

Microarchitectural channels Microarch events (e.g., timing, perf. counters, etc.) Victim Victim Victim Attacker

6.888 L4-Covert and Side Channels 11

slide-23
SLIDE 23

Power Analysis

from https://en.wikipedia.org/wiki/Power_analysis

6.888 L4-Covert and Side Channels 12

slide-24
SLIDE 24

Victim Application: RSA

  • Square-and-multiply based exponentiation

Input : base b, modulo m, exponent e = (en−1 ...e0 )2 Output: be mod m r = 1 for i = n−1 down to 0 do r = sqr(r) r = mod(r,m) if ei == 1 then r = mul(r,b) r = mod(r,m) end end return r

6.888 L4-Covert and Side Channels 13

slide-25
SLIDE 25

Victim Application: RSA

  • Square-and-multiply based exponentiation

Input : base b, modulo m, exponent e = (en−1 ...e0 )2 Output: be mod m r = 1 for i = n−1 down to 0 do r = sqr(r) r = mod(r,m) if ei == 1 then r = mul(r,b) r = mod(r,m) end end return r

6.888 L4-Covert and Side Channels 13

slide-26
SLIDE 26

Power Analysis

6.888 L4-Covert and Side Channels 14

slide-27
SLIDE 27

Power Analysis

  • Various signal processing

techniques to de-noise.

  • More advanced: differential

power analysis (DPA)

6.888 L4-Covert and Side Channels 14

slide-28
SLIDE 28

Benign Usage: Non-intrusive Software Monitoring

  • How to efficiently monitor

application for anomaly detection?

Sehatbakhsh et al. Spectral Profiling: Observer-Effect-Free Profiling by Monitoring EM Emanations. MICRO’16

6.888 L4-Covert and Side Channels 15

slide-29
SLIDE 29

Benign Usage: Non-intrusive Software Monitoring

  • How to efficiently monitor

application for anomaly detection?

Sehatbakhsh et al. Spectral Profiling: Observer-Effect-Free Profiling by Monitoring EM Emanations. MICRO’16

6.888 L4-Covert and Side Channels 15

slide-30
SLIDE 30

What can you do with these channels?

  • Violate privilege boundaries
  • Inter-process communication
  • Infer an application’s secret
  • (Semi-Invasive) application profiling

6.888 L4-Covert and Side Channels 16

slide-31
SLIDE 31

What can you do with these channels?

  • Violate privilege boundaries
  • Inter-process communication
  • Infer an application’s secret
  • (Semi-Invasive) application profiling

Different from traditional software or physical attacks:

  • Stealthy. Sophisticated mechanisms needed to detect channel
  • Usually no permanent indication one has been exploited

6.888 L4-Covert and Side Channels 16

slide-32
SLIDE 32

uArch Side Channels

slide-33
SLIDE 33

Recap: Process Isolation

Virtual Address Space (Programmer's View) Physical Address Space (limited by DRAM size) 4KB 4KB VA PA Page Table per process Process 1 Process 2 4KB 4KB

6.888 L4-Covert and Side Channels 18

slide-34
SLIDE 34

Recap: Process Isolation

Virtual Address Space (Programmer's View) Physical Address Space (limited by DRAM size) 4KB 4KB VA PA Page Table per process Process 1 Process 2 4KB 4KB

How to communicate across processes?

6.888 L4-Covert and Side Channels 18

slide-35
SLIDE 35

Normal Cross-process Communication

include <socket.h> void send(bit msg) { socket.send(msg); } bit recv() { return socket.recv(msg); }

6.888 L4-Covert and Side Channels 19

slide-36
SLIDE 36

Normal Cross-process Communication

include <socket.h> void send(bit msg) { socket.send(msg); } bit recv() { return socket.recv(msg); }

How to communication without letting OS know?

6.888 L4-Covert and Side Channels 19

slide-37
SLIDE 37

Normal Cross-process Communication

include <socket.h> void send(bit msg) { socket.send(msg); } bit recv() { return socket.recv(msg); }

How to communication without letting OS know?

  • -> Use HW contention

6.888 L4-Covert and Side Channels 19

slide-38
SLIDE 38

Covert Channels 101: Through the Page Fault

Process 1 (Sender) Process 2 (Receiver)

DRAM (limited size) 4KB 4KB

6.888 L4-Covert and Side Channels 20

slide-39
SLIDE 39

Covert Channels 101: Through the Page Fault

Process 1 (Sender) Process 2 (Receiver)

if (send ‘1’) accesses many pages else idle

DRAM (limited size) 4KB 4KB

6.888 L4-Covert and Side Channels 20

slide-40
SLIDE 40

Covert Channels 101: Through the Page Fault

Process 1 (Sender) Process 2 (Receiver)

t1 = rdtsc() Accesses many pages t2 = rdtsc() if (send ‘1’) accesses many pages else idle if (t2 – t1 > THRESH) read ‘1’ else read ‘0’

DRAM (limited size) 4KB 4KB

6.888 L4-Covert and Side Channels 20

slide-41
SLIDE 41

Cache: # ways # sets

Another Example of Using Caches

Process 1 (Sender) Process 2 (Receiver)

t1 = rdtsc() Fill up the cache t2 = rdtsc() if (send ‘1’) Fill up the cache else idle if (t2 – t1 > THRESH) read ‘1’ else read ‘0’

6.888 L4-Covert and Side Channels 21

slide-42
SLIDE 42

Faster Communication

Process 1 (Sender) Process 2 (Receiver)

t1 = rdtsc() Fill set i t2 = rdtsc() if (send ‘1’) Fill set i else idle if (t2 – t1 > THRESH) read ‘1’ else read ‘0’ Cache: # ways # sets

6.888 L4-Covert and Side Channels 22

slide-43
SLIDE 43

Generalizes to Channels Beyond Caches

Hardware resource Sender Receiver

t1 = rdtsc() Use resource t2 = rdtsc() if (send ‘1’) Use resource else idle if (t2 – t1 > THRESH) read ‘1’ else read ‘0’

6.888 L4-Covert and Side Channels 23

slide-44
SLIDE 44

HW Resource Contention

Processor Chip (socket) core

L1/L2

core

L1/L2

LLC … System Bus (logically) Processor Chip (socket) core

L1/L2

core

L1/L2

LLC … Memory (DRAM)

  • ther I/O Devices

Non-volatile storage device

6.888 L4-Covert and Side Channels 24

slide-45
SLIDE 45

The Memory Hierarchy

  • L1, L2
  • Shared by threads on the same core
  • LLC:
  • Shared by threads on different cores
  • Directory:
  • Shared by threads on different sockets
  • DRAM row buffer:
  • Shared by …..

Processor Chip (socket) core

L1/L2

core

L1/L2

LLC … Memory (DRAM) Processor Chip (socket) core

L1/L2

core

L1/L2

LLC …

6.888 L4-Covert and Side Channels 25

slide-46
SLIDE 46

The Memory Hierarchy

  • L1, L2
  • Shared by threads on the same core
  • LLC:
  • Shared by threads on different cores
  • Directory:
  • Shared by threads on different sockets
  • DRAM row buffer:
  • Shared by …..

Processor Chip (socket) core

L1/L2

core

L1/L2

LLC … Memory (DRAM) Processor Chip (socket) core

L1/L2

core

L1/L2

LLC …

Cache is a popular attack target. Why?

6.888 L4-Covert and Side Channels 25

slide-47
SLIDE 47

Protocol 101: Prime+Probe in the Cache

Shared Cache

Sender Receiver

Cache Set

# ways

6.888 L4-Covert and Side Channels 26

slide-48
SLIDE 48

Prime+Probe

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

# ways

6.888 L4-Covert and Side Channels 27

slide-49
SLIDE 49

Prime+Probe – Send “1”

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

Wait Access

# ways

6.888 L4-Covert and Side Channels 28

slide-50
SLIDE 50

Prime+Probe – Send “1”

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

Wait Access

# ways

6.888 L4-Covert and Side Channels 28

slide-51
SLIDE 51

Prime+Probe – Send “1”

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

Wait Access

# ways

6.888 L4-Covert and Side Channels 28

slide-52
SLIDE 52

Prime+Probe – Receive “1”

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

Wait Access

# ways

Receive “1” = 16 accesses à 1 miss

Probe

6.888 L4-Covert and Side Channels 29

slide-53
SLIDE 53

Prime+Probe – Send “0”

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

# ways

NO Access Wait

6.888 L4-Covert and Side Channels 30

slide-54
SLIDE 54

Prime+Probe – Receive “0”

Shared Cache

Sender Receiver

Sender line Receiver line

Time Prime

Cache Set

# ways

NO Access Wait

Receive “0” = 16 accesses à 0 miss

Probe

6.888 L4-Covert and Side Channels 31

slide-55
SLIDE 55

A Complete Protocol -- Synchronization

Prime Wait Probe

Sample window length

  • Window size agreed on by sender and receiver
  • Each window transmits some bits
  • Sender & receiver need to perform an window alignment at the start

Receiver Receiver Sender

6.888 L4-Covert and Side Channels 32

slide-56
SLIDE 56

A Complete Protocol -- Synchronization

Prime Wait Probe Prime Wait Probe

Sample window length

  • Window size agreed on by sender and receiver
  • Each window transmits some bits
  • Sender & receiver need to perform an window alignment at the start

Receiver Receiver Sender

6.888 L4-Covert and Side Channels 32

slide-57
SLIDE 57

A Complete Protocol -- Synchronization

Prime Wait Probe Prime Wait Probe

Sample window length

  • Window size agreed on by sender and receiver
  • Each window transmits some bits
  • Sender & receiver need to perform an window alignment at the start

Receiver Receiver Sender

6.888 L4-Covert and Side Channels 32

Question: how to distinguish between noise and actual transmission?

slide-58
SLIDE 58

Bandwidth

Error-free bitrate of send() à recv() Depends on what hardware structure is used to build the channel. send(msg) recv()

Channel

6.888 L4-Covert and Side Channels 33

slide-59
SLIDE 59

Bandwidth

Error-free bitrate of send() à recv() Depends on what hardware structure is used to build the channel.

  • RDRAND unit: 7-200 Kbps [EP’16]
  • Ld/st performance counters: ~75-150 Kbps [HKRVDT‘15]
  • MemBus/AES-NI contention: ~550-650 Kbps [HKRVDT‘15]
  • LLC: 1.2 Mbps [MNHF’15]
  • Various structures on GPGPU: up to 4 Mbps [NKG’17]

send(msg) recv()

Channel

6.888 L4-Covert and Side Channels 33

slide-60
SLIDE 60

From Covert à Side Channels

Hardware resource Victim Attacker

if (send ‘1’) Use resource else idle Covert channel: t1 = rdtsc() Use resource t2 = rdtsc() if (t2 – t1 > THRESH) read ‘1’ else read ‘0’

6.888 L4-Covert and Side Channels 34

slide-61
SLIDE 61

From Covert à Side Channels

Hardware resource Victim Attacker

if (send ‘1’) Use resource else idle Covert channel: t1 = rdtsc() Use resource t2 = rdtsc() if (t2 – t1 > THRESH) read ‘1’ else read ‘0’

6.888 L4-Covert and Side Channels 34

slide-62
SLIDE 62

From Covert à Side Channels

Hardware resource Victim Attacker

if (send ‘1’) Use resource else idle Covert channel: if (secret) Use resource else idle Side channel: t1 = rdtsc() Use resource t2 = rdtsc() if (t2 – t1 > THRESH) read ‘1’ else read ‘0’

6.888 L4-Covert and Side Channels 34

slide-63
SLIDE 63

Micro-architecture Side Channels

Transient + Any structure e.g., RamBleed, RIDDLE

uArch Side Channels

Transient + Cache e.g, Foreshadow Spectre/ Meltdown Non-transient + Any structure

6.888 L4-Covert and Side Channels 35

slide-64
SLIDE 64

Side Channels Targeting Different Structures

On-chip Processor Off-chip DRAM

core

L1/L2

L3 core

L1/L2

… …

Flush+Reload, Prime+Probe Directory Attacks RNG Unit Covert Chanel CacheOut, RIDL, Fallout Port contention, cache banking, 4K Alias RowHammer, DRAMA RAMBleed

Spectre, Meltdown

Foreshadow, Arithmetic timing

6.888 L4-Covert and Side Channels 36

slide-65
SLIDE 65

Next Lecture: Non-transient µArch Side Channels

slide-66
SLIDE 66

6.888 L4-Covert and Side Channels 38

Hard Disk Drive (HDD)