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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Cost Efficient Hardware Timestamping Intermediate Presentation - - PowerPoint PPT Presentation
Cost Efficient Hardware Timestamping Intermediate Presentation - - PowerPoint PPT Presentation
Chair of Network Architectures and Services Department of Informatics Technical University of Munich Cost Efficient Hardware Timestamping Intermediate Presentation Alexander Frank June 6, 2018 Chair of Network Architectures and Services
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Motivation
For conducting high precision latency measurements one currently has the following options:
- Proprietary solutions (e.g. DAG Packet Capture Cards from endace1)
- NetFPGAs
For this IDP we take a different approach using only commodity hard- ware The Intel Xeon Processor D-1500 family offers 10 GbE connections based on X552 Ethernet Controllers → able to timestamp arbitrary packets
1https://www.endace.com/endace-high-speed-packet-capture-solutions/oem/dag/ Frank – Networking 3
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Current set-up
Narva Klaipeda Tilga Splitter
Figure 1: All connections are optical fiber based, splitters are completely passive and do disturb communication
Frank – Networking 4
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Explanation – Klaipeda, Narva
Klaipeda Narva
Figure 2: Narva (Generator) and Klaipeda (DuT)
Narva:
- MoonGen and DPDK as gen-
erator
- Generates up to 10 Gbit/s
- Rate limiter to achieve desired
bit rate Klaipeda:
- MoonGen forwarder
- Open vSwitch
- Any other forwarding/routing
software
Frank – Networking 5
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Explanation – Tilga
Tilga
Figure 3: Sniffer, captures and/or timestamps packets
Tilga features an X552 which allows timestamping of arbitrary packets
- Captures packets
- Inserts hardware timestamps
- Optionally
handles post- processing The cables from Tilga to the splitter box have the same length → no relative error
Frank – Networking 6
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Packet Matching
Table Size Table Size Port 1 Packet ID: 1 Packet ID: 2 Port 0 Sniffer: Tilga Packet ID: 4 Packet ID: 5 Packet ID: 5 Packet ID: 3 Packet ID: 3 Packet ID: 3 Latency Hardware Timestamp Headers (e.g. Eth, IPv4, UDP) Payload with ID Packet ID: 3 ≥ 5 Bytes 8 Byte Table with 2^28 Entries 10 Gbit/s ≈ 14.88 mpps Table size = 2^28 Entries => Max. latency ≈ 18 sec Higher latencies with increased table size Pre DuT Post DuT
Frank – Networking 7
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Operation Modes
- 1. Online
Latency is computed during capture operation. Low accuracy.2
- 2. Offline Timestamps Only
Latency is computed in a separate processing step. During cap- ture only the timestamps and IDs are saved. High accuracy.2
- 3. Offline Packet Capture
All incoming packets are captured. Postprocessing tries to find matching packets according to user-defined function. High accu- racy.
2Requires packet payload to contain an ID Frank – Networking 8
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Comparison
Device Timestamp Resolution Ports Price (USD) User friendly? Endace DAG 10X2-S3 4 ns 2 2500
()
NetFPGA SUME4 6.25 ns 4 4100 X Intel Xeon CPU D-15375 12.5 ns 2 570
- Conclusion: Using commodity hardware we achieve reasonable pre-
cise timestamps for a fraction of the cost
3https://www.endace.com/endace-high-speed-packet-capture-solutions/oem/dag/ 4https://netfpga.org/site/#/systems/1netfpga-sume/details/ 5https://ark.intel.com/de/products/91196/Intel-Xeon-Processor-D-1537-12M-Cache-1_70-GHz Frank – Networking 9
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Baseline – 30 m fiber cable
Frank – Networking 10
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Next Steps
Modes: Online Done Offline Timestamps Only Done Offline Packet Capture WIP Other: Post-processing Done Automated Measurement Series Done Documentation Pending
Frank – Networking 11
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich
Questions and Suggestions?
Frank – Networking 12
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Chair of Network Architectures and Services Department of Informatics Technical University of Munich