Control with binary code William Sandqvist william@kth.se Dec Bin - - PowerPoint PPT Presentation

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Control with binary code William Sandqvist william@kth.se Dec Bin - - PowerPoint PPT Presentation

Oct 01, 2023 572 likes •1.31k views

Control with binary code William Sandqvist william@kth.se Dec Bin Hex Oct 218 10 = 11011010 2 = DA 16 = 332 8 William Sandqvist william@kth.se Ex 1.1c Decimal to Binry binary weights: 1024 512 256 128 64 32 16 8 4 2 1 71 10 = ?

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SLIDE 1

William Sandqvist william@kth.se

Control with binary code

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SLIDE 2

William Sandqvist william@kth.se

Dec – Bin – Hex – Oct

21810 = 110110102 = DA16 = 3328

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SLIDE 3

Ex 1.1c Decimal to Binäry

William Sandqvist william@kth.se

7110 = ?2

binary weights: 1024 512 256 128 64 32 16 8 4 2 1

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SLIDE 4

William Sandqvist william@kth.se

7110 = ?2 7110 = (64+7= 64+4+2+1) =10001112

Ex 1.1c Decimal to Binäry

binary weights: 1024 512 256 128 64 32 16 8 4 2 1

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SLIDE 5
  • Ex. 1.2a Binary to Decimal

William Sandqvist william@kth.se

1011010012 = ?10

binary weights: 1024 512 256 128 64 32 16 8 4 2 1

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SLIDE 6

William Sandqvist william@kth.se

1011010012 = ?10 1011010012 = (28+26+25+23+20=256+64+32+8+1) =36110

  • Ex. 1.2a Binary to Decimal

binary weights: 1024 512 256 128 64 32 16 8 4 2 1

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SLIDE 7

Ex 1.3c Binary/Octal/Hexadecimal

William Sandqvist william@kth.se

1001101012 = ?16 = ?8

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SLIDE 8

William Sandqvist william@kth.se

1001101012 = ?16 = ?8 1 0011 01012 = 1 3 516 Ex 1.3c Binary/Octal/Hexadecimal

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SLIDE 9

William Sandqvist william@kth.se

1001101012 = ?16 = ?8 1 0011 01012 = 1 3 516 100 110 1012 = 4 6 58 Ex 1.3c Binary/Octal/Hexadecimal

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SLIDE 10

Venn-diagram

William Sandqvist william@kth.se

x in common with y x together with y x in common with outside y

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SLIDE 11
  • Ex. 3.2 De Morgans theorem

with Venn diagram

William Sandqvist william@kth.se

Prove De Morgans theorem with the use of Venn Diagram.

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SLIDE 12
  • Ex. 3.2 De Morgan

William Sandqvist william@kth.se

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SLIDE 13
  • Ex. 3.2 De Morgan

William Sandqvist william@kth.se

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SLIDE 14
  • Ex. 3.2 De Morgan

William Sandqvist william@kth.se

=

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SLIDE 15
  • Ex. 3.2 De Morgan

William Sandqvist william@kth.se

=

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SLIDE 16
  • Ex. 3.2 De Morgan

William Sandqvist william@kth.se

=

Now proved!

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SLIDE 17

William Sandqvist william@kth.se

(Ex. 5.1) How to open the code-lock? (=minterm)

Which buttons should be simultaneously pressed in

  • rder to light up the lamp?

( = open up the lock)

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SLIDE 18

William Sandqvist william@kth.se

Answer: 4,d and 2,h but you must simultaneously avoid pressing a b c e f g i and k! Which buttons should be simultaneously pressed in

  • rder to light up the lamp?

( = open up the lock)

(Ex. 5.1) How to open the code-lock? (=minterm)

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SLIDE 19

William Sandqvist william@kth.se

Answer: 4,d and 2,h but you must simultaneously avoid pressing a b c e f g i and k! Which buttons should be simultaneously pressed in

  • rder to light up the lamp?

( = open up the lock)

(Ex. 5.1) How to open the code-lock? (=minterm)

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SLIDE 20

William Sandqvist william@kth.se

Answer: 4,d and 2,h but you must simultaneously avoid pressing a b c e f g i and k! Which buttons should be simultaneously pressed in

  • rder to light up the lamp?

( = open up the lock)

(Ex. 5.1) How to open the code-lock? (=minterm)

A product-term with all variables is called a minterm.

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SLIDE 21

Ex 3.3 Venn Diagram

William Sandqvist william@kth.se

a) Draw a Venn Diagram for thre variables and mark all truth table minterms in the diagram. b) Minimize this function with the help of the Venn Diagram.

1 2 1 2 1 2 1 2 1 2

x x x x x x x x x x x x x x x f + + + + =

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SLIDE 22
  • Ex. 3.3a Truth Table – Venn diagram

William Sandqvist william@kth.se

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SLIDE 23
  • Ex. 3.3b simplified expression

William Sandqvist william@kth.se

Orginal expression.

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SLIDE 24
  • Ex. 3.3b simplified expression

William Sandqvist william@kth.se

Simplified! Orginal expression.

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SLIDE 25

William Sandqvist william@kth.se

Boole’s algebra rules

Logical addition "+", OR, and logical multiplication "×", AND, broadly follows the usual normal algebraic distributive, commutative and associative laws (with one exception).

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SLIDE 26

William Sandqvist william@kth.se

Theorems

Rules

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SLIDE 27
  • Ex. 4.1(a, b, c, h) Boolean

algebra

William Sandqvist william@kth.se

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SLIDE 28
  • Ex. 4.1a

William Sandqvist william@kth.se

d a d c a f ⋅ + ⋅ ⋅ = d a c d a factor d a d c a f ⋅ = + ⋅ ⋅ = = ⋅ + ⋅ ⋅ = ) 1 ( } ad {

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SLIDE 29
  • Ex. 4.1b

William Sandqvist william@kth.se

a b b a b a b a b a a c a a b a b a c a b a f = + ⋅ = ⋅ + + = = ⋅ ⋅ + ⋅ ⋅ + ⋅ = ⋅ + ⋅ + ⋅ = ) ( ) (

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SLIDE 30
  • Ex. 4.1c

William Sandqvist william@kth.se

f a b a b c = + + ⋅ + =

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SLIDE 31
  • Ex. 4.1c

William Sandqvist william@kth.se

( ) ( ) ... ... 1 f a b a b c a a a b a b c a a b a b a b c a a b a b b c a a = + + ⋅ + = + + ⋅ + ⋅ + = = + ⋅ + ⋅ + ⋅ + = = + ⋅ + ⋅ + + = = + =

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SLIDE 32
  • Ex. 4.1h

William Sandqvist william@kth.se

( ) f a a b = + ⋅ =

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SLIDE 33
  • Ex. 4.1h

William Sandqvist william@kth.se

b a b a a deMorgan b a a f + = + + = = ⋅ + = } { ) (

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SLIDE 34
  • Ex. 4.4 De Morgan

William Sandqvist william@kth.se

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SLIDE 35
  • Ex. 4.4

William Sandqvist william@kth.se

c b c a a a c b b b c a c b a bc a c b a c b a c b a bc a c b a c b a c b a c b a c b a c b a c b a c b c b a c b a c b a c b c b a c b a c b a + = + + + = = + + + = + + = + + + + + + + + = + + + + + + = = + + + + + + + = + + + + + + ) ( ) ( ) ( ) ( ) ( ) )( )( ( ) )( )( ( ) )( )( ( Duplicate!

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SLIDE 36

Logic gates

William Sandqvist william@kth.se

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SLIDE 37

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 38

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

AND Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 39

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

AND OR 1 Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 40

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

AND OR 1 XOR Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 41

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

AND OR 1 XOR NAND Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 42

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

AND OR 1 XOR NAND NOR 1 Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 43

William Sandqvist william@kth.se

(Ex. 4.5a) Gates

AND OR 1 XOR NAND NOR 1 XNOR 1 Enter the name and output 1/0 for the following six gate types when the input signals are as shown in the figure.

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SLIDE 44
  • Ex. 4.7 Timing diagram and

Truth Table

William Sandqvist william@kth.se

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  • Ex. 4.7

William Sandqvist william@kth.se

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  • Ex. 4.7

William Sandqvist william@kth.se

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  • Ex. 4.7

William Sandqvist william@kth.se

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  • Ex. 4.7

William Sandqvist william@kth.se

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  • Ex. 4.12 From text to Boolean

equations

William Sandqvist william@kth.se

A combinatorical circuit with six input signals x5, x4, x3, x2, x1 and three output signals u2, u1, u0, is described in this way:

  • u0 = 1 if and only if ”either both x0 and x2 are 0 or x4 and x5 are different”
  • u1 = 1 if and only if ”x0 and x1 are equal and x5 is the inverse of x2”
  • u2 = 0 if and only if ”x0 is 1 and some of x1 … x5 is 0”
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SLIDE 50

ÖH 4.12

William Sandqvist william@kth.se

u0 = 1 if and only if ” either both x0 and x2 are 0

  • r x4 and x5 are different”

XOR AND XOR

) (

5 4 2

x x x x u ⊕ ⊕ ⋅ =

NOT

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SLIDE 51

ÖH 4.12

William Sandqvist william@kth.se

u1 = 1 if and only if ” x0 and x1 are equal and x5 is the inverse of x2 ”

XNOR AND XOR

) ( ) ( ) (

2 5 2 5 1 1 2 5 1 1

x x x x x x x x x x x x u + ⋅ + = ⊕ ⋅ ⊕ =

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SLIDE 52

ÖH 4.12

William Sandqvist william@kth.se

u2 = 0 if and only if ” x0 is 1 and some of x1 … x5 is 0 ”

NOT AND OR NOT

5 4 3 2 1 5 4 3 2 1 5 4 3 2 1 2 5 4 3 2 1 2

) ( ) ( ) ( x x x x x x x x x x x x x x x x x x u x x x x x x u ⋅ ⋅ ⋅ ⋅ + = = + + + + + = = + + + + ⋅ = ⇒ + + + + ⋅ =

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SLIDE 53

William Sandqvist william@kth.se

Logic circuits of SoP-form

All the logical functions can be realized by using gate types AND and OR combined in two steps. We assume here that the input variables are also available in inverted form, if not then you of course inverters too.

One can realize the gate circuit direct from the truth table. Each "1" in the table is a minterm. The function is the sum of these

  • minterms. One says that the

function is expressed in the SoP form (Sum of Products).

However, there may exist a simpler circuit with fewer gates that do the same job.

AND-OR logic, SoP-form

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  • Ex. 5.2 SoP and PoS normal form

William Sandqvist william@kth.se

A locic function has this Truth Table: Write the function on SoP normal form: Write the function on PoS normal form:

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SLIDE 55

William Sandqvist william@kth.se

  • Ex. 5.2 SoP-form

A logical function has the following truth table. Specify the function of SoP-normal form (sum of products).

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SLIDE 56

William Sandqvist william@kth.se

  • Ex. 5.2 SoP-form

A logical function has the following truth table. Specify the function of SoP-normal form (sum of products).

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SLIDE 57

William Sandqvist william@kth.se

c b a c b a c b a c b a f ⋅ ⋅ + ⋅ ⋅ + ⋅ ⋅ + ⋅ ⋅ =

  • Ex. 5.2 SoP-form

A logical function has the following truth table. Specify the function of SoP-normal form (sum of products).

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SLIDE 58

William Sandqvist william@kth.se

c b a c b a c b a c b a f ⋅ ⋅ + ⋅ ⋅ + ⋅ ⋅ + ⋅ ⋅ =

  • Ex. 5.2 SoP-form

A logical function has the following truth table. Specify the function of SoP-normal form (sum of products).

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William Sandqvist william@kth.se

Logik circuits of PoS-form

Thus, if the function is to be "0" for a particular variable combination (a, b) for example (0.0) one is forming the sum (a + b). This sum could only be "0" for the combination (0.0). Such a sum is called a maxterm. The function is expressed as a product of all such maxtermer. Each maxterm contributes with a 0 from the truth-table. The function is said to be expressed in the PoS form (Product of Sums). Alternatively, one can focus on the truth table 0s. If a gate circuit reproduces the function 0's correct then of course the 1's are right to!

OR-AND logic, PoS form

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SLIDE 60

William Sandqvist william@kth.se

  • Ex. 5.2 PoS-form

A logical function has the following truth table. Specify the function of PoS-normal form (product of sums).

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SLIDE 61

William Sandqvist william@kth.se

  • Ex. 5.2 PoS-form

A logical function has the following truth table. Specify the function of PoS-normal form (product of sums).

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SLIDE 62

William Sandqvist william@kth.se

) ( ) ( ) ( ) ( c b a c b a c b a c b a f + + ⋅ + + ⋅ + + ⋅ + + =

  • Ex. 5.2 PoS-form

A logical function has the following truth table. Specify the function of PoS-normal form (product of sums).

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SLIDE 63

William Sandqvist william@kth.se

) ( ) ( ) ( ) ( c b a c b a c b a c b a f + + ⋅ + + ⋅ + + ⋅ + + =

  • Ex. 5.2 PoS-form

A logical function has the following truth table. Specify the function of PoS-normal form (product of sums).

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SLIDE 64

William Sandqvist william@kth.se

∑ and Π

SoP and PoS-forms are usually simplifies to a list of the included maxtermerm’s / mintermerm’s serial number: f(a,b) = ∑m(1,2) f(a,b) = ΠM(0,3)

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SLIDE 65
  • Ex. 5.3 SoP and PoS -form

William Sandqvist william@kth.se

A minimized function is given on SoP form (Sum of Products). Specify this function with minterms on SoP normal form, and with maxterms on PoS (Product of Sums) normal form.

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SLIDE 66
  • Ex. 5.3

William Sandqvist william@kth.se

∏ ∑ ∑

+ + + + = = ⇒ = = ⇒ + + + + + = = + + + + + = + + = ) )( ( ) 7 , ( ) , , ( ) 6 , 5 , 4 , 3 , 2 , 1 ( ) 110 , 101 , 100 , 011 , 010 , 001 ( ) , , ( ) ( ) ( ) ( ) , , ( z y x z y x M z y x f m m z y x f z y x yz x z y x z xy z y x z y x z y y x z y x x z z y x z x z y y x z y x f

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SLIDE 67

William Sandqvist william@kth.se

complete logic NAND-NAND

OR AND and NOT could be produces with NAND gates. For logic functions on the SoP form, you can change the AND-OR circuit to NAND-NAND "straight

  • ff".

The cost, the number of gates, will be the same!

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SLIDE 68

William Sandqvist william@kth.se

complete logic NOR-NOR

OR AND and NOT can also be produced with NOR gates. For logic functions on the PoS form, you can replace the OR- AND circuit to NOR-NOR "straight off".

The cost, the number of gates, will be the same!

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SLIDE 69
  • Ex. 5.5 NAND-gates

William Sandqvist william@kth.se

Change to NAND gates!

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  • Ex. 5.5

William Sandqvist william@kth.se

c b a c b a c b a ⋅ ⋅ = ⋅ + = ⋅ +

?

&

c b a

&

Algebraically: Change to NAND gates

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SLIDE 71

(Ex. 4.11) European and American Symbols

William Sandqvist william@kth.se

Try out yourself …

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SLIDE 72

William Sandqvist william@kth.se

(Ex. 4.11) European and American Symbols

Try out yourself …