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Computationally Complete Spiking Neural P Systems Without Delay: - - PowerPoint PPT Presentation

Computationally Complete Spiking Neural P Systems Without Delay: Two Types of Neurons Are Enough Rudolf Freund 1 , Marian Kogler 1 , 2 1 Faculty of Informatics, Vienna University of Technology, Austria 2 Institute of Computer Science, Martin


slide-1
SLIDE 1

Computationally Complete Spiking Neural P Systems Without Delay: Two Types of Neurons Are Enough

Rudolf Freund1, Marian Kogler1,2

1 Faculty of Informatics, Vienna University of Technology, Austria 2 Institute of Computer Science, Martin Luther University Halle-Wittenberg,

Germany Email: rudi@emcc.at, marian@emcc.at, kogler@informatik.uni-halle.de

CMC11

slide-2
SLIDE 2

Overview

Preliminaries Results Suggestions for Future Work

slide-3
SLIDE 3

Register Machines

Definition (Register Machine)

A register machine is a construct M = (n, B, p0, ph, I) where

  • 1. n, n ≥ 1, is the number of registers,
  • 2. B is the set of instruction labels,
  • 3. p0 is the start label,
  • 4. ph is the halting label (only used for the HALT instruction) and
  • 5. I is a set of (labeled) instructions.
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SLIDE 4

Register Machines

Definition (Register Machine (ctd.))

Instructions are of the following forms:

◮ pi : (ADD(r), pj, pk) increments the value in register r and

continues with one of the instructions labeled by pj and pk, chosen in a nondeterministic way,

◮ pi : (SUB(r), pj, pk) tries to decrement the value in register r;

if the register was non-empty before the instruction, the computation continues with the instruction labeled with pj, if not, it continues with the instruction pk;

◮ ph : HALT halts the machine.

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SLIDE 5

Register Machines

Definition (Register Machine (ctd.))

◮ Deterministic register machines can be constructed by

imposing the condition pj = pk on ADD-instructions.

◮ We will be using nondeterministic register machines as

generators and deterministic register machines as acceptors.

◮ Every recursively enumerable set of (vectors of) natural

numbers with k components can be generated with only k + 2 registers, where the first k registers are never decremented (Minsky, 1967).

slide-6
SLIDE 6

Spiking Neural P Systems (Without Delays)

Definition (Spiking neural P system)

A spiking neural P system (without delays) is a construct Π = (O, ρ1, ..., ρn, syn, in, out) where

  • 1. O = {a} is the (unary) set of objects (the object a is called

spike),

  • 2. ρ1, ..., ρn are the neurons, where ρi = (di, Ri) for 1 ≤ i ≤ n,

with di being the initial configuration of the neuron i and Ri being the set of rules,

  • 3. in is the input neuron (with the only function to spike once in

generating spiking neural P systems in order to start a computation), and

  • 4. out is the output neuron (no function in accepting spiking

neural P systems).

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SLIDE 7

Spiking Neural P Systems (Without Delays)

Definition (Spiking neural P system (ctd.))

Possible forms for the rules:

◮ E/ai → aj, where E is a regular expression over O and

i, j ≥ 1 (firing rules) or

◮ ai → λ, where i ≥ 1 (forgetting rules). There must not be any

rule ai → λ such that ai ∈ L(E) for some E of a firing rule.

◮ syn ⊆ {1, ..., n} × {1, ..., n} are the synapses, where

(i, j) ∈ syn indicates a synapse from i to j,

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SLIDE 8

Spiking Neural P Systems (Without Delays)

Definition (Spiking neural P system (ctd.))

◮ A spiking neural P system inputs and outputs numbers via a

spike train. A spike train starts with a spike given in step t1 and ends with a spike given in step t2. The number is specified by t2 − t1 − 1, i.e., the number of steps that elapse between the two spikes. It accepts an input by a series of configurations, starting from the initial configuration and ending in a halting configuration.

◮ Rules of the form E/ai → aj where L(E) is finite (infinite) are

called bounded (unbounded) rules.

◮ Two neurons ρi and ρj are of the same type if and only if

Ri = Rj, di = dj and |{(i, k) ∈ sym | k ∈ {1, ..., n}}| = |{(j, k) ∈ sym | k ∈ {1, ..., n}}|.

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SLIDE 9

Results

◮ Accepting spiking neural P systems (without delays) with only

two types of neurons are computationally complete.

◮ Generating spiking neural P systems without delays with only

two types of neurons are computationally complete.

◮ Corollary: Spiking neural P systems without delays with only

three neurons with unbounded rules are computationally complete.

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SLIDE 10

Results

◮ Accepting spiking neural P systems (without delays) with only

two types of neurons are computationally complete.

◮ Generating spiking neural P systems without delays with only

two types of neurons are computationally complete.

◮ Corollary: Spiking neural P systems without delays with only

three neurons with unbounded rules are computationally complete.

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SLIDE 11

The Two Types

λ a/a → a a2 → λ a3/a3 → a a4/a4 → a a5 → λ Type 1 λ a → λ a3(a2)∗/a3 → a Type 2

slide-12
SLIDE 12

A Dummy Structure

d1 d2 d3

❅ ❅ ❘

d4

❅ ❅ ❘

d5

❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ☛ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❑ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✕

slide-13
SLIDE 13

A Dummy Structure

d1 d2 d3

❅ ❅ ❘

d4

❅ ❅ ❘

d5

❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ☛ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❑ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✕

a

slide-14
SLIDE 14

A Dummy Structure

d1 d2 d3

❅ ❅ ❘

d4

❅ ❅ ❘

d5

❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ☛ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❑ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✕

a a

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SLIDE 15

A Dummy Structure

d1 d2 d3

❅ ❅ ❘

d4

❅ ❅ ❘

d5

❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ☛ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❑ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✕

aa aa

slide-16
SLIDE 16

A Dummy Structure

d1 d2 d3

❅ ❅ ❘

d4

❅ ❅ ❘

d5

❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ☛ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❆ ❑ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✁ ✕

slide-17
SLIDE 17

Simulating an ADD-instruction

pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

✚✙ ✛✘ ✚✙ ✛✘ ❄ ❄

pj D

slide-18
SLIDE 18

Simulating an ADD-instruction

pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

✚✙ ✛✘ ✚✙ ✛✘ ❄ ❄

pj D a

slide-19
SLIDE 19

Simulating an ADD-instruction

pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

✚✙ ✛✘ ✚✙ ✛✘ ❄ ❄

pj D a a

slide-20
SLIDE 20

Simulating an ADD-instruction

pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

✚✙ ✛✘ ✚✙ ✛✘ ❄ ❄

pj D aa a a

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SLIDE 21

Simulating a SUB-instruction

p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-22
SLIDE 22

Simulating a SUB-instruction

... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-23
SLIDE 23

Simulating a SUB-instruction

aa a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-24
SLIDE 24

Simulating a SUB-instruction

aa a a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-25
SLIDE 25

Simulating a SUB-instruction

a a aaa p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-26
SLIDE 26

Simulating a SUB-instruction

a a a a a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-27
SLIDE 27

Simulating a SUB-instruction

a a a a a ... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-28
SLIDE 28

Simulating a SUB-instruction

aa aa a aa aa ... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-29
SLIDE 29

Simulating a SUB-instruction

a ... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-30
SLIDE 30

Simulating a SUB-instruction

a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-31
SLIDE 31

Simulating a SUB-instruction

a a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-32
SLIDE 32

Simulating a SUB-instruction

a a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-33
SLIDE 33

Simulating a SUB-instruction

a a p11 pn1 pi1 ... ... pi2 pi3 pi4 pi5 r

❄ ❄ ❍❍❍❍ ❥ ❄ ❄ ❄

... ... ...

❄ ❄

... ... ... ... ... ... p′

11

p′

i1

p′

n1

˜ pi1 ˜ pi2

❄ ❄ ❄ ❄

slide-34
SLIDE 34

Simulating a SUB-instruction

a a a ... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-35
SLIDE 35

Simulating a SUB-instruction

aa a aa ... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-36
SLIDE 36

Simulating a SUB-instruction

a ... ˜ pi4 ˜ pi5 p′

i2

p′

i3

... ... p′

if

p′

is

❄ ❄ ❄ ❄ ❄❄ ✚✙ ✛✘ ✚✙ ✛✘

pis pif

❄ ❄

❅ ❅ ❅ ❅ ❘

˜ pi3

✛ ✲

slide-37
SLIDE 37

Initialization

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-38
SLIDE 38

Initialization

a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-39
SLIDE 39

Initialization

a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-40
SLIDE 40

Initialization

a a a a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-41
SLIDE 41

Initialization

a a a a aa a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-42
SLIDE 42

Initialization

a a a a aa aa a a a a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-43
SLIDE 43

Initialization

aa a a a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-44
SLIDE 44

Initialization

aa a a aa a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-45
SLIDE 45

Initialization

aa a a aa a a a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-46
SLIDE 46

Initialization

aa aa aa

aaaa

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-47
SLIDE 47

Initialization

aa a

in i1 i2 i3 i4 r1

❅ ❅ ❘ ❄ ❄ ❅ ❅ ❘

✛ ✲ ✁ ✁ ✁ ✁ ✁ ✁ ☛

i6 i7 i8 i9 i5 i10

❆ ❆ ❯ ✁ ✁ ☛ ❆ ❆ ❯ ❄ ✁ ✁ ☛ ◗◗ ◗ s

i11 i12

✁ ✁ ☛ ❆ ❆ ❯ ✛ ✲

i13

❄ ❆ ❆ ❆ ❆ ❆ ❆ ❯ ✏ ✏ ✏ ✏ ✏ ✮

✒✑ ✓✏

p0

slide-48
SLIDE 48

Results

◮ Accepting spiking neural P systems (without delays) with only

two types of neurons are computationally complete.

◮ Generating spiking neural P systems without delays with only

two types of neurons are computationally complete.

◮ Corollary: Spiking neural P systems without delays with only

three neurons with unbounded rules are computationally complete.

slide-49
SLIDE 49

The Two Types (Modified for Nondeterminism)

λ a/a → a a2 → λ a3/a3 → a a4/a4 → a a5 → λ a6/a6 → a a6/a6 → a2 Type 1 λ a → λ a3(a2)∗/a3 → a Type 2

slide-50
SLIDE 50

Simulating a non-deterministic ADD-instruction

pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-51
SLIDE 51

Simulating a non-deterministic ADD-instruction

a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-52
SLIDE 52

Simulating a non-deterministic ADD-instruction

a a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-53
SLIDE 53

Simulating a non-deterministic ADD-instruction

aa a a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-54
SLIDE 54

Simulating a non-deterministic ADD-instruction

aa a a a a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-55
SLIDE 55

Simulating a non-deterministic ADD-instruction

aa a a a a a a a a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-56
SLIDE 56

Simulating a non-deterministic ADD-instruction

aa aaa aaa a a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-57
SLIDE 57

Simulating a non-deterministic ADD-instruction

aa aa a aa

a aa

pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-58
SLIDE 58

Simulating a non-deterministic ADD-instruction

aa a a pi1 pi2 pi3

❅ ❅ ❘

r

❅ ❅ ❘

pi4 pi5 pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 pi14 pi15 pi16 pi17 pi18 pi19 pi20

✒✑ ✓✏

pj pi22 pi21

✒✑ ✓✏

pk

❄ ❏ ❏ ❏ ❫ ✡ ✡ ✡ ✢ ❄ ❳❳❳❳❳ ③ ◗◗ ◗ s ◗◗ ◗ s ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✘ ✘ ✘ ✘ ✾ ✟ ✟ ✟ ✙ ❄ ❄ ✛ ✲ ❄ ❄ ✟ ✟ ✟ ✙ ✘ ✘ ✾ ✚ ✚ ✚ ❂ ✏ ✏ ✏ ✏ ✏ ✏ ✮ PP P q ✛

slide-59
SLIDE 59

Output

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-60
SLIDE 60

Output

aa a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-61
SLIDE 61

Output

aa a a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-62
SLIDE 62

Output

aa a a a a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-63
SLIDE 63

Output

aaaaa a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-64
SLIDE 64

Output

aaa a a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-65
SLIDE 65

Output

a a a a a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-66
SLIDE 66

Output

a a aa a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-67
SLIDE 67

Output

a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-68
SLIDE 68

Output

a

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7

r1

  • 8
  • 9
  • 11
  • 10
  • ut

❄ ❄ ❍ ❍ ❥ ✏ ✏ ✏ ✮ ❄ ❄ ❄ ❍❍ ❍ ❥ ❄ ✻ ❄ ✛ ✑ ✑ ✑ ✰ ✻ ◗◗ ◗ s ❄ ❄ ❄ ❄

slide-69
SLIDE 69

Results

◮ Accepting spiking neural P systems (without delays) with only

two types of neurons are computationally complete.

◮ Generating spiking neural P systems without delays with only

two types of neurons are computationally complete.

◮ Corollary: Spiking neural P systems without delays with only

three neurons with unbounded rules are computationally complete.

slide-70
SLIDE 70

Suggestions for Future Work

◮ Which ingredients are needed to generalize the results for

recursively enumerable sets of vectors of natural numbers?

◮ Which changes in the constructions of the proofs elaborated

in this paper are necessary if the input (in the accepting case)

  • r the output (in the generating case) are initially (finally)

given as contents of an unbounded input (output) neuron?

◮ To which number of neurons with unbounded rules can the

constructions in the proofs elaborated in this paper be reduced when simulating universal register machines (using spike trains with three spikes to introduce the code of the machine to be simulated as well as its input)?

◮ For all these variants of spiking neural P systems without

delay, is one type of (unbounded) neurons sufficient?

slide-71
SLIDE 71