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CISC Design: Implementation from HFC Virendra Singh Associate - - PowerPoint PPT Presentation

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CISC Design: Implementation from HFC Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail:

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CISC Design:

Implementation from HFC

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

EE-739: Processor Design

Lecture 8 (29 Jan 2013)

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Level 2 Flowcharts

Tasks Access Type ALU and CC Duplicates Page and Loc State ID Synonym Acess Width Next State Label A Label B

Format for Level 2 flowchart state

  • DR – Data Read
  • DW – Data Write
  • IR - Instruction Read
  • NA – No aceess
  • BC – Branch conditionally
  • IB – Instruction branch
  • SB – Sequence branch
  • StateID – Direct branch
  • S – Set
  • N – Not set
  • X – Don’t care
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Level 2 Flowchart: Address Mode Sequences

Base Plus Displacement edb  di pc  a  alu, ao +1  alu di  b  alu ry  a  alu t1  a  pc edb  di t1  b  ao, t2

ir add-n abdm1 abdm2 na x-n abdm2 abdm3 na add-n dr x-n abdm3 abdm4 abdm4 sb

(RY+d)@

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Merged Level 2 Flowchart: Address Mode Sequences

Base Plus Displacement edb  di pc  a  alu, ao +1  alu di  b  alu ry  a  alu t1  a  pc edb  di t1  b  ao, t2

ir add-n abdm1 abdm2 na x-n abdm2 abdm3 na add-n dr x-n abdm3 abdm4 abdm4 sb

(RY+d)@

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Merged Level 2 Flowchart: Address Mode Sequences

Register Indirect edb  di ry  b  ao, t2

dr x-n adrm1 sb

RY@

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Merged Level 2 Flowchart: Address Mode Sequences

edb  irf pc  a  alu, ao +1  alu irf  ire t1  b  pc edb  irf ry  a  alu, ao +1  alu Branch Instruction

Z = 1 (Branch) Z = 0 (no branch)

ir add-n brzz1 bc na x-n brzz2 ib ir add-n brzz3 brzz2

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Merged Level 2 Flowchart: Execution Sequences

Execution sequences with memory operand reference di  b  rx, t2 edb  irf pc  a  alu, ao +1  alu irf  ire t1  b  pc t2  a  alu 0  alu

LOAD

ir add-x ldrm1 ldrm2 ldrm2 ib na add-s

Mem  RX

rx  a  alu, do t2  b  ao 0  alu

STORE

dw add-s strm1 brzz3

Mem  RX

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Merged Level 2 Flowchart: Execution Sequences

Execution sequences with memory operand reference di  b  alu rx  a  alu

ADD, AND, SUB

t1  a  do t2  b  ao

na

  • p-s

dw x-s

  • prm1
  • prm2
  • prm2

brzz3 RX OP Mem  Mem

di  b  t2 edb  irf pc  a  alu, ao +1  alu

TEST

ir add-x test1 ldrm2

Mem  ALU

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Merged Level 2 Flowchart: Execution Sequences

Execution sequences for Register-to-Register and special instructions rx  a  alu ry  b  alu

ADD, SUB, AND

Edb  irf Pc  a  alu, ao T1  a  ry +1  alu

na

  • p-s

ir add-n

  • prr1
  • prr2
  • prr2

brzz2

RX OP RY  RY

LOAD

edb  irf pc  a  alu, ao ry  a  rx, t2 +1  alu

ir add-x ldrr1 ldrm2

RX  RY

Edb  irf Pc  a  alu, ao Rx  b  ry, t2 +1  alu

STORE ir add-x strr1 ldrm2

RX  RY

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Merged Level 2 Flowchart: Execution Sequences

Execution sequences for Register-to-Register and special instructions edb  di ry  a  alu, ao +1  alu

POP

Di  b  rx T1  a  ry

dr add-n popr1 popr2 popr2 brzz3 na x-n

RY@  RX RY+1  RY

ry  a  alu

  • 1  alu

PUSH

rx  a  do t1  b  ao, ry

na add-n dw x-n push2 brzz3 push1 push2

RY-1  RY RY@  RX

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Processor Block Diagram

IB

Datapath

Control Store Next State Control Branch Control Instruction Decoder IRE IRF

Control word Decoders

Control Fields (Static) OP TY NA SB B C D B Condition Codes Control lines Control Fields (dynamic) Control Word Register

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MIN Datapath

AO PC T2 R0 R1 Rn T1 ALU DO DI IRF IRE k

Internal A Bus Internal B Bus External Address Bus (EAB) External Data Bus (EDB)

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Implementation

 Each state in Level 2 flowchart corresponds to one

control word

 Transformation of flowcharts into control store bit

patterns

  • The task become bits in the control fields (OP)
  • The next state becomes in the control store address

select (TY) and next address (NA)

  • The state ID becomes the location of the control

word in the control store

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Implementation

Relationship between Flowcharts and Hardware

 Flowchart – compact and precise description of

hardware requirements

 Stepts for implementing microcoded controller

  • 1. Execution Unit

Develop concurrently

Add things as and when needed

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Implementation

  • 2. Instruction Decoders

 Translate an instruction bit pattern to the control

store address for the execution sequence

 Two decoders are needed (for MIN)  First, translates the instruction bit pattern into

the control store address for the appropriate address mode sequence (provide IB)

 Second, translates the instruction bit pattern into

control store address for the execution sequence (provide SB)

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Implementation

  • 3. Control word format
  • Derived from flowcharts
  • HFC can tell required capability of control word

precisely 4. Control word decoders

  • Combine control word (dynamic) control fields,

the IRE (static) control fields, and timing signals, to provide the gate control signals for all transfers in the Datapath and the Controller

  • 5. Controller block diagram
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Implementation

 Design of flowchart

  • Made some assumptions (buses, registers..)
  • Collect the assumptions and implement
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MIN Datapath

AO PC T2 R0 R1 Rn T1 ALU DO DI IRF IRE k

Internal A Bus Internal B Bus External Address Bus (EAB) External Data Bus (EDB)

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Instruction Decoders

Two decoders

First Decoder (IB decoder)

  • Points to the first control word in an address

mode sequence (if there is one)

  • The last state in any execution sequence is IB

 Second Decoder (SB decoder)

  • Points to the first control word of the execution

sequence

  • The last sequence in addr. mode seq. is SB
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Instruction Execution Sequences

Instruction Control Word Sequence Next control word address IB Instruction Decoder SB Instruction Decoder

POP popr1 popr2 brzz3 brzz2 popr2 brzz3 brzz2

  • abdm1
  • prm1

ADD RX(RY+d)@ abdm1 abdm2 abdm3 abdm4

  • prm1
  • prm2

brzz3 brzz2 abdm2 abdm3 abdm4

  • prm2

brzz3 brzz2

  • prr1
  • prm1
  • prm1
  • prm1
  • prm1
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Instruction Execution Sequences

Instruction Control Word Sequence Next control word address IB Instruction Decoder SB Instruction Decoder SUB RX RY

  • prr1
  • prr2

brzz2

  • prr2

brzz2

  • adrm1
  • test1

TEST RY@ adrm1 test1 ldrm2

  • ldrm2
  • adrm1
  • push1

test1

  • PUSH
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IB Instruction Decoder

IB Decoder Address Instruction(s) or Address Mode abdm1 (RY+d)@ Address mode sequences adrm1 RY@ brzz1 BZ Execution sequences (Instructions without separate address mode sequences) ldrr1 LR strr1 STR

  • prr1

AR, SR, NR popr1 POP push1 PUSH

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SB Instruction Decoder

SB Decoder Address Instruction(s) or Address Mode ldrm1 L Execution sequences (Instructions with separate address mode sequences) strm1 ST

  • prm1

A, S, N test1 T

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Control Word Format

Control words

  • Operation section (OP) is composed of the

fields for Datapath control

  • Next state section, containing TY and NA,

contains the field for state sequencer control

  • If two macro in the Datapath are never used at

the same time, you might consider sharing the control field

OP TY NA

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MIN Control Word

AO PC T2 R0 R1 Rn T1 ALU DO DI IRF IRE k

Internal A Bus Internal B Bus (EAB) (EDB)

AO PC T2 …. Regs T1 ALU K DI DO IRE IRF Control Fields

MIN Execution Unit

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Control Word Decoder

 How many bits each control needs?  Procedure

  • 1. List uses of the macro
  • 2. Allocate bits
  • 3. Use a Karnaugh map to assign bit patterns

 Collect all the occurrences (PC, T2, RX …)  Assign no. of bits to control fields

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Control Word Decoder

 PC Control

  • PC occurrences
  • pc  a
  • a  pc (only one occurrence – abdm2)
  • b  pc
  • none
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PC Control

none Pc  a x b  pc pcb pca 1 1

PC

pca pcb Internal A Bus Internal B Bus

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Control Word Decoder

 T2 Control

  • T2 occurrences
  • t2  a
  • t2  b
  • a  t2 (only one occurrence – abdm4)
  • b  t2
  • None
  • Assign two bits (4 occurrences)
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T2 Control

none T2  a T2  b B  t2 t2b t2a 1 1

t2b . t2a a2a . t2b

T2

a2a . t2b Internal A Bus Internal B Bus

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Control Word Decoder

 Register control

  • RX and RY occurrences

ry  a b rx ry  b; b  rx rx  a rx  b; b  ry rx  a; ry  b b ry b  rx; a  ry rx  a; b  ry none

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Register Control

r0b R0

Internal A Bus Internal B Bus

MUX r0a r0 r0a/ br0

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Register Control

OP RX Mode RY AO PC T2 Regs T1 ……

Control Word register Control Field Decoder

MUX n-to-2n Decoder

r ra rb ar/br r0 rn r1 r2

Instruction (from IRE) Control word (from Control Store)

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Register Control

OP RX Mode RY AO PC T2 Regs T1 ……

Control Word RX register Control Field Decoder ry rya

n-to-2n RY Decoder

y0 yn y1 y2

Instruction (from IRE) Control word (from Control Store) n-to-2n RX Decoder

x0 xn x1 x2 Control Word RY register Control Field Decoder brx rxa rxb ryb ary/bry

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Control Word Decoder

 Register control

 r0 = (b  rx).x0 + ( ry). y0 load r0 a r0 = (b  rx).x0 + ((a  ry)/(b  ry)’). y0 load from A r0 a = (rx  a).x0 + (ry  a). y0 to A r0 b = (rx  b).x0 + (ry  b). y0 to B

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Control Word Decoder

 Control Word States

ry  a b  rx ry  b; b  rx Rx  a Rx  b; b  ry rx  a; ry  b b  ry b  rx; a  ry rx  a; b  ry none ry  a b  rx;  rx ry  b;  rx; b  rx rx  a rx  b;  ry; b  ry rx  a; ry  b b  ry;  ry b  rx;  ry; a  ry;  ry rx  a;  ry; b  ry none

 Control Lines

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Control Word Decoder

 Control Lines rx  a ry  a rx  b ry  b  rx  ry a  ry b  rx b  ry

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Register Control

none b  rx b  ry 00 00 01 ry  a rx  b b  ry rx  a b  ry rx  a 01 11 10

1 3 2 4 5 7 6

b  rx a  ry b  rx ry  b 11 10 rx  a ry  b

12 13 15 14 8 9 11 10

b  ry  ry a  ry b  rx rx  a  rx

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Control Word Decoder

 Control Word States

None b  rx ry  a rx  a b  ry rx  b; b  ry rx  a; b  ry ry  b; b  rx rx  a; ry  b b  rx; a  ry

 Control Bit Assignment

  • 0000
  • 0001
  • 0010
  • 0011
  • 0100
  • 0110
  • 0111
  • 1001
  • 1011
  • 1101
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Control Word Decoder

 Control Lines rx  a ry  a rx  b ry  b  rx  ry a  ry b  rx b  ry

  • xx11
  • 0010
  • 0110
  • 10xx
  • xx01
  • x1xx
  • 11xx
  • xx01
  • 01xx

 Decoder Patterns

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Register Control

OP RX Mode RY AO PC T2 Regs T1 ……

Control Word RX register Control Field Decoder brr

n-to-2n B Decoder

r0 rn r1 r2 Instruction (from IRE) Control word (from Control Store)

n-to-2n A Decoder

r0 rn r1 r2 Control Word RY register Control Field Decoder arr rra rrb MUX MUX

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Thank You

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