CIS 314 Introduction to Digital Logic Prof. Michel A. Kinsy - - PowerPoint PPT Presentation

Computer and Information Science

CIS 314

Introduction to Digital Logic

• Prof. Michel A. Kinsy

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Systems & Computing Systems

• A system is a set of related components that

works as a whole to achieve a goal

• A system contains:
• Inputs
• Behavior
• Outputs
• Behavior is a function that translates inputs to
• utputs

Behavior inputs

• utputs

: :

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

System Components

• Components are electronic blocks: analog,

digital, and mixed signal

• Analog system has values from a continuous set

+5

• 5

V Time

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

System Components

• Components are electronic blocks: digital,

analog, and mixed signal

• Digital system is a system in which signals have a finite

number if discrete values

+5

• 5

V 1 1 Time

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Transistors

• MOS - Metal-Oxide Semiconductor
• MOS transistors have three terminals: drain,

gate, and source

• A transistor acts as switches:
• if the voltage on the gate terminal is higher/lower than

the source terminal then a conducting path will be established between the drain and source terminals

G S D G S D n-channel p-channel

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Transistors

• CMOS - Complementary MOS
• Transistors are the primary

components of ICs

• An integrated circuit (IC) or a chip is

made up of transistors (these days billions) and other electronic components

• ICs are the building blocks of

computers (CPU, bus interface, memory management unit)

O I Vss Vdd

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Transistors

Architecture Transistor Count Year Maker Technolog y Size Intel 4004 2,300 1971 Intel 10μm Intel 8008 3,500 1972 Intel 10μm Quad-core 2,000,000,000 2010 Intel 65nm 61-core Xeon Phi 5,000,000,000 2012 Intel 22nm Xbox One 5,000,000,000 2013 Microsoft/AM D 28nm 18-core Xeon Haswell-E5 5,560,000,000 2014 Intel 22nm

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Computer & Digital Design

• Boolean algebra serves as the basis for

computer logic design

• Transistors are the mean to implement Boolean

algebra in modern computer systems

• Basic Boolean algebra
• Set of Elements: {0,1}
• Set of Operations: {., + , ¬ }
• Digital equivalence
• Signals: High = 5V = 1; Low = 0V = 0

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Boolean Algebra to Digital Design

x 1 1 y 1 1 F 1 x 1 1 y 1 1 F 1 1 1 x 1 F 1 x y F OR F x y AND 1 y x x y F 1 F x F x N O T Symbol/Gate Truth table Transistor circuit 1 x y F y x

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Logic Gates

X = (A + B)’

Name Symbol Function Truth Table

AND 0 0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 OR NOT X = A’ NAND X = (AB)’ NOR XOR Exclusive OR X = A  B Or X = A’B + AB’ X = (A  B)’

• r

X = A’B’+ AB XNOR Exclusive NOR

• r Equivalence

A B X

A B X 0 1 1 0 A X 0 0 1 0 1 1 1 0 1 1 1 0 A B X 0 0 1 0 1 0 1 0 0 1 1 0 A B X 0 0 0 0 1 1 1 0 1 1 1 0 A B X 0 0 1 0 1 0 1 0 0 1 1 1 A B X X = A • B

• r

X = AB A B X A B X X = A + B A X A B X A B X A B X A B X

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Boolean Algebra to Digital Design

• Addition
• Truth Table

1 0 0 1 0 1 0 1 Sum 1 1 1 0 Carry 0 0 0 1 A B Cin Sum Cout

0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Boolean Algebra to Digital Design

• Truth Table
• Equations

A B Cin Sum Cout

0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Sum = Cin . A’ . B’ + B . Cin’ . A’ + A . Cin’ . B’ + A . B . Cin Cout = A’ . B . Cin + A . B’ . Cin + A . Cin’ . B + B . Cin . A = A . B + A . Cin + B . Cin

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Boolean Algebra to Digital Design

Sum = Cin . A’ . B’ + B . Cin’ . A’ + A . Cin’ . B’ + A . B . Cin

A B Cin Sum

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Boolean Algebra to Digital Design

Cout = A’ . B . Cin + A . B’ . Cin + A . Cin’ . B + B . Cin . A = A . B + A . Cin + B . Cin

A B Cin Cout

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Types of Digital Circuits

• Combinatorial logic
• A combinational circuit consists of logic gates whose
• utputs, at any time, are determined by combining the

values of the inputs

• Sequential logic
• Output depends not only on the present value of its

input signals but on the sequence of past inputs

Combinational Circuits inputs x

• utputs

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Types of Digital Circuits

• Sequential logic
• Output depends not only on the present value of its

input signals but on the sequence of past inputs

• We now have a memory requirement!

Combinational Circuits inputs x

• utputs

Memory next state present state

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Memory & Digital Design

• A sequential circuit combinational circuit with

feedback through memory

• The stored information at any time defines a state
• Outputs depends on inputs and previous inputs
• Previous inputs are stored as binary information into

memory

• Next state depends on inputs and present state

Combinational Circuits inputs x

• utputs

Memory next state present state

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Types of Digital Circuits

• Sequential logic
• Storage elements observe inputs and can change state
• nly in relation to a timing signal
• Need for discrete instances of time
• We now have a clock requirement!

CLOCK

Combinational Circuits inputs x

• utputs

Memory next state present state

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Clock

• A synchronous system is synchronized according

to a clock

• A clock cycle or cycle time or clock period is the

duration between two consecutive rising or falling edges

Cycle time Rising clock edge Falling clock edge 4 GHz = clock speed = 1 = 1 cycle time 250 ps

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Storage Elements (Memory)

• A storage element can maintain a binary state

(0,1), until directed by an input signal to switch state

• Main difference between storage elements:
• Number of inputs they have
• How the inputs affect the binary state

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Storage Elements (Memory)

• A storage element can maintain a binary state

(0,1), until directed by an input signal to switch state

• Two main types:
• Latches (level-sensitive)
• Flip-Flops (edge-sensitive)
• Latches are useful in asynchronous sequential

circuits

• Flip-Flips are built with latches

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Latches & Flip Flops

• A latch is binary storage element
• Can store a 0 or 1
• The most basic memory
• Easy to build
• Built with gates (NORs, NANDs, NOT)

S’R’ Latch SR Latch SR Latch with Clock D Latch

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Latches & Flip Flops

• A flip flop can be built using two latches in a

master-slave configuration

• A master latch receives external inputs
• A slave latch receives inputs from the master

latch

• Depending on the clock signal, only one latch is

active at any given time

• If clock=1, the master latch is enabled and the inputs

are latched

• if clock=0, the master is disabled and the slave is

activated to generate the outputs

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Computer Hardware Elements

• Combinational circuits
• Mux, Demux, Decoder, ALU, ...
• Synchronous state elements
• Flipflop, Register, Register file, SRAM, DRAM
• Edge-triggered: Data is sampled at the rising edge

Clk D Q En ff Q D Clk En

Sel O A0 A1 An-1 Mux

. . .

lg(n)

Sel

O0 O1 On-1

A Demux

. . .

lg(n)

A Decoder

. . .

O0 O1 On-1

lg(n)

OpSelect

• Add, Sub, ...
• And, Or, Xor, Not, ...
• GT, LT, EQ, Zero, ...

Result Comp? A B

ALU

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

A Simple Memory Model

• Reads and writes are always completed in one

cycle

• a Read can be done any time (i.e. combinational)
• a Write is performed at the rising clock edge
• If it is enabled Then the write address and data must be

stable at the clock edge

MAGIC RAM ReadData WriteData Address WriteEnable Clock

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Circuit Complexity Classes

• SSI - Small-Scale Integration
• Several (less than 10) independent gates
• MSI - Medium-Scale Integration
• 10 to 200 gates
• LSI - Large-Scale Integration
• 200 to few thousand gates
• VLSI - Very-Large-Scale Integration
• Thousands to Billions of gates

Computer Architecture and Embedded Systems Laboratory (CAES Lab)

Next Class

• Arithmetic Logic Unit (ALU) and Register File