Chapter 7 Utilities for High-Level Descriptions 1 Type - - PowerPoint PPT Presentation

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Chapter 7

Utilities for High-Level Descriptions

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Type Declarations and Usage

• Enumeration types
• Physical types
• Array types
• Record types

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Enumeration Types

• Enumeration is basic scalar type
• Enumeration is defined as set of all

possible values that such a type may have

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Enumeration Type Declaration

TYPE type_name IS (element {,element}); TYPE qit IS (‘0’ ,’1’ ,’Z’, ‘X’);

• Enumeration elements are case sensitive
• Default initial value is left-most element

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Four-Value Inverter

USE WORK.basic_utilities.ALL; ENTITY inv_q IS GENERIC(tplh:TIME;tphl:TIME); PORT(i1:IN qit;o1:OUT qit); END; ARCHITECTURE qq OF inv_q IS BEGIN

• 1<=‘1’ AFTER tplh WHEN i1=‘0’ ELSE

‘0’ AFTER tphl WHEN i1=‘1’ OR i1=‘Z’ ELSE ‘X’ AFTER tplh; END;

Condition

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Four-Value NAND Gate

USE WORK.basic_utilities.ALL; ENTITY nand_q IS GENERIC(tplh:TIME;tphl:TIME); PORT(i1,i2:IN qit;o1:OUT qit); END; ARCHITECTURE qq OF nand_q IS BEGIN

• 1<=‘1’ AFTER tplh WHEN i1=‘0’ OR i2=‘0’ ELSE

‘0’ AFTER tphl WHEN (i1=‘1’ OR i1=‘1’) OR (i1=‘1’ OR i1=‘Z’) OR (i1=‘Z’ OR i1=‘1’) OR (i1=‘Z’ OR i1=‘Z’) ELSE ‘X’ AFTER tplh; --UNAFFECTED END;

X 1 1 X 1 1 X X 1 X X 1 Z 1 1 1 X Z

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Type Conversion

NewType(expression)

• INTEGER(2.5*5.1) -- 12
• REAL(3) --3.0

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Type Conversion

USE WORK.basic_utilities.ALL; ENTITY inv_q IS GENERIC(c_load: REAL := 0.066E-12); PORT(i1:IN qit;o1:OUT qit); CONSTANT rpu :REAL := 25000.0; CONSTANT rpd :REAL := 15000.0; END; ARCHITECTURE qq OF inv_q IS CONSTANT tplh : TIME := INTEGER(rpu*c_load *1.0E15) * 3 FS; CONSTANT tphl : TIME := INTEGER(rpd*c_load *1.0E15) * 3 FS; BEGIN

• 1<=‘1’ AFTER tplh WHEN i1=‘0’ ELSE

‘0’ AFTER tphl WHEN i1=‘1’ OR i1=‘Z’ ELSE ‘X’ AFTER tplh; END;

Visible to All Architectures of inv_q

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Physical Type Declaration

TYPE capacitance IS RANGE 0 TO 1E16 UNITS ffr; pfr= 1000 ffr; nfr= 1000 pfr; ufr= 1000 nfr; mfr= 1000 ufr; far= 1000 mfr; kfar= 1000 far; END UNITS;

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Physical Type Declaration

TYPE resistance IS RANGE 0 TO 1E16 UNITS l_o;

• hms= 1000 l_o;

k_o= 1000 ohms; m_o= 1000 k_o; g_o= 1000 m_o; END UNITS;

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Physical Type Usage

USE WORK.basic_utilities.ALL; ENTITY inv_q IS GENERIC(c_load: capacitance := 66 ffr); PORT(i1:IN qit;o1:OUT qit); CONSTANT rpu :resistance := 25 k_o; CONSTANT rpd :resistance := 15 k_o; END; ARCHITECTURE qq OF inv_q IS CONSTANT tplh : TIME := ( (rpu/ 1 i_o)*(c_load/ 1 ffr) ) * 3 FS /1000; CONSTANT tphl : TIME := ( (rpd/ 1 i_o)*(c_load/ 1 ffr) ) * 3 FS /1000; BEGIN

• 1<=‘1’ AFTER tplh WHEN i1=‘0’ ELSE

‘0’ AFTER tphl WHEN i1=‘1’ OR i1=‘Z’ ELSE ‘X’ AFTER tplh; END;

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Array Type Declaration

TYPE arry_name IS ARRAY range OF element_type TYPE qit_nibble IS ARRAY (3 DOWNTO 0) OF qit; TYPE qit_byte IS ARRAY (1 DOWNTO 8) OF qit; TYPE qit_word IS ARRAY (1 DOWNTO 16) OF qit; TYPE byte IS ARRAY (7 DOWNTO 0) OF BIT;

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Array Type Declaration

TYPE qit_mem IS ARRAY ( 0 TO 7 ) OF qit_nibble;

TYPE mem IS ARRAY( 0 TO 3) OF byte;

TYPE mem2 IS ARRAY (3 DOWNTO 0,0 TO 7) OF BIT;

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Array Initialization

SIGNAL x: qit_byte := ( 5=>’Z’ , OTHERS=>’1’);

SIGNAL x: qit_byte := ( 1 DOWNTO 0=>’Z’ ,3 TO 4=>’X’ ,OTHERS=>’1’); SIGNAL x: qit_byte := (OTHERS=>’Z’);

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2-D Array Initialization

SIGNAL m:mem2:=( (‘0’,’1’,’1’,’1’,’1’,’0’,’1’,’Z’), (‘0’,’1’,’1’,’0’,’1’,’0’,’1’,’Z’), (‘Z’,’1’,’0’,’1’,’1’,’0’,’1’,’Z’), (‘1’,’1’,’1’,’0’,’1’,’0’,’1’,’Z’), ); SIGNAL m:mem2:=(OTHERS=>”01010101”); SIGNAL m:mem2:=(OTHERS=>(OTHERS=>’Z’));

SIGNAL m:mem2:=(OTHERS=>(0 TO 1 =>’1’,OTHERS=>’0’));

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Array Indexing

SIGNAL x8: qit_byte; SIGNAL x16: qit_word; SIGNAL mq:qit_mem; SIGNAL m:mem2;

… x8<=x16(11 downto 4); x16(15 downto 12) <=x8(4 downto 1); (x8(1),x8(3),x8(2))<=x16(10 downto 8); x8<=x16(1)& x16(3)& x16(2)& x16(15 downto 11); mq(1)<=x8; mq(3)(5)<=x16(3); X16(10 downto 8)<=mq(4)(3 DOWNTO 1); X8(1)<=to_qt ( m(2,5) );

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Noninteger Indexing

TYPE qit_2d IS ARRAY(qit,qit) OF qit; CONSTANT qit_nand2 :qit_2d :=(

• - ‘0’ ‘1’ ‘Z’ ‘X’

(‘1’,’1’,’1’,’1’) –’0’ (‘1’,’0’,’0’,’X’) –’1’ (‘1’,’0’,’0’,’X’) –’Z’ (‘1’,’X’,’X’,’X’) –’X’ );

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Noninteger Indexing

USE WORK.basic_utilities.ALL; ENTITY nand2 IS PORT(i1,i2:IN qit;o1:OUT qit); END; ARCHITECTRE table_based OF nand2 IS BEGIN

• 1<= qit_nand2(i1,i2) AFTER 10 NS;

END;

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Noninterger Indexing

CONSTANT qit_nand2:qit_2d :=( ‘0’ => (OTHERS=>’1’), ‘X’ => (‘0’ => ‘1’ , OTHERS=> ‘X’), OTHERS =>(‘0’ =>’1’ ,’X’ =>’1’,OTHERS=>’0’) );

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Unconstrained Arrays

TYPE BIT_VECTOR IS ARRAY (NATURAL RANGE <>) OF BIT; TYPE STRING IS ARRAY (POSITIVE RANGE <>) OF BIT;

TYPE INTEGER_VECTOR IS ARRAY (NATURAL RANGE <>) OF INTEGER; Type mark

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File Type

• VHDL standard package provides file i/o
• perations
• Default file type is text file
• Users can define their own file types

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File Type Declaration

TYPE logic_data IS FILE OF CHARACTERS;

TYPE std_file Is FILE OF std_logic_vector(7 downto 0);

TYPE type_name IS FILE OF element_type

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FILE Declaration

FILE file_name : file_type [OPEN mode] [IS physical_file_name]; Kind ::= READ_MODE | WRITE_MODE|APPEND_MODE;

FILE inp1 : logic_data; FILE inp2 : logic_data IS “input.dat”; FILE inp3 : logic_data OPEN READ_MODE IS “input.dat”;

Open file in READ_MODE

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File Operations – Open/Close

FILE_OPEN(file_var,physical_file_name,mode) FILE_CLOSE(file_var);

FILE_OPEN(inp1,”input.dat”,WRITE_MODE); FILE_OPEN(inp2,”input.dat”,READ_MODE); FILE_OPEN(inp3,”input.dat”); … FILE_CLOSE(inp1); FILE_CLOSE(inp2);

READ_MODE is default

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FILE Operations – End of File

ENDFILE(file_var)

• Returns TRUE if subsequent operation

can not be done from the file

WHILE NOT ENDFILE(f1) LOOP

• -Some FILE operations on f1

END LOOP;

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FILE I/O

READ(file_var,variable); WRITE(file_var,variable);

• Type of variable must be same as file type
• All file operations are sequential

WRITE(f1,”01010100”); Signal a:std_logic_vector(7 downto 0); READ(f1,a);

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FILE I/O Example

PROCEDURE assign_bits( SIGNAL s:OUT BIT; file_name: IN STRING; period : IN TIME) IS VARIABLE char :CHARACTER; VARIABLE current: TIME:=0 NS; FILE iput_value_file : logic_data; BEGIN FILE_OPEN(input_value_file,file_name,READ_MODE); WHILE NOT ENDFILE(input_value_file) LOOP READ(input_value_file,char); IF char=‘0’ OR char=‘1’ THEN current:=current+period; IF char=‘0’ THEN s<=TRANSPORT ‘0’ AFTER current; ELSIF char=‘1’ THEN s<=TRANSPORT ‘1’ AFTER current; END IF; END IF; END LOOP; END;

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VHDL Operators

• Logical
• Relational
• Shift
• Adding
• Sign
• Aggregate
• NOTA

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Logical Operators

• AND,NAND,NOR,OR,XOR,XNOR,NOT

x<=a xnor b; x_vector<=a_vector AND b_vector; x<=“xnor” (a , b); x_vector<=“AND” (a_vector, b_vector);

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Relational

• Relational Operators return Boolean Type
• >,<,>=,<=,/=,=

a_boolean<=i1 > i2; if ( i1/=i2) then … a_vector < b_vector

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Shift

Logical Logical Arith Logical Arith Logical Logical/Arith Right Left Left Right Left Left Left/Right Rotate Rotate Shift Shift Shift Shift Shift/Rotate ROR ROL SRA SRL SLA SLL

A<= b SLL 2; B<= c ROL –3;

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Adding and Multiplying and NOTA

• Addition(+),Subtraction(-) , Concatenation(&)

a<= b+c; a<=b & c;

• Multiply(*), Divide(/), MOD, REM

a<= b REM c;

• Exponential(**), ABS

a<= b**5; b<= ABS(d);

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Aggregate

• Same as concatenation

(a,b)<=“10”; (a,b)<=a2; (a,b)<=(‘1’,’0’); c_vector<=(“101”,’1’,’1’&’0’);

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Operator Overloading

• Operators can be represented by their

strings c<=a AND b; c<=“AND” (a,b);

• Each subprogram with different types of

parameters can be distinguished from each other

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NAND Overloading

FUNCTION “NAND” (a,b:qit) RETURN qit IS CONSTANT qit_nand2 :qit_2d :=(

• - ‘0’ ‘1’ ‘Z’ ‘X’

(‘1’,’1’,’1’,’1’) –’0’ (‘1’,’0’,’0’,’X’) –’1’ (‘1’,’0’,’0’,’X’) –’Z’ (‘1’,’X’,’X’,’X’) –’X’ ); BEGIN return qit_nand2(a,b); END;

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Not Overloading

TYPE qit_1d IS ARRAY(qit) OF qit; … FUNCTION “NOT” (a:qit) RETURN qit IS CONSTANT qit_not :qit_1d :=(‘1’,’0’,’0’,’X’); BEGIN return qit_not(a); END;

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RC Calculation

PACKAGE basic_utilities IS TYPE capacitance … TYPE resistance … FUNCTION “*” (a:resistance;b:capacitance) RETURN TIME; END; PACKAGE BODY basic_utilities IS FUNCTION “*” (a:resistance;b:capacitance) RETURN TIME IS BEGIN RETURN (( a/ 1 l_o) * ( b / 1 ffr) * 1 FS) / 1000; END; END;

SIGNAL c:capacitance; SIGNAL r:resistance;

• 1<= i1 and i2 AFTER r*c;

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Case Statement

• Multiple if –elsif statements cam be replaced by

Case statement

• Var can be from each type with defined “=“
• perator

CASE var IS WHEN equality1 => statements WHEN equality2 => statements WHEN equalityn => statements WHEN OTHERS => statements END CASE;

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Assign_bits Using CASE

PROCEDURE assign_bits( SIGNAL s:OUT qit; file_name: IN STRING; period : IN TIME) IS VARIABLE char :CHARACTER; VARIABLE current: TIME:=0 NS; FILE iput_value_file : logic_data; BEGIN FILE_OPEN(input_value_file,file_name,READ_MODE); WHILE NOT ENDFILE(input_value_file) LOOP READ(input_value_file,char); current:=current+period; CASE char IS WHEN ‘0’ => s<=TRANSPORT ‘0’ AFTER current; WHEN ‘1’ =>s<=TRANSPORT ‘1’ AFTER current; WHEN ‘Z’ =>s<=TRANSPORT ‘Z’ AFTER current; WHEN ‘X’ =>s<=TRANSPORT ‘X’ AFTER current; WHEN OTHERS => current:=current-period; END CASE; END LOOP; END;