Chapter 5 General Architecture of Computer CPU - MEM - I/O - - PDF document

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Chapter 5 General Architecture of Computer CPU - MEM - I/O - - PDF document

Jul 30, 2023 413 likes •509 views

Outline Chapter 5 General Architecture of Computer CPU - MEM - I/O Peripheral Computer Organization Memory Hierarchy Main Memory Auxiliary Memory Process Control Input-Output Interface Flaxer Eli - Process Control

slide-1
SLIDE 1

Flaxer Eli - Process Control

Ch 5 - 1

Chapter 5 Computer Organization

Process Control

Flaxer Eli - Process Control

Ch 5 - 2

Outline

General Architecture of Computer

– CPU - MEM - I/O – Peripheral

Memory Hierarchy

– Main Memory – Auxiliary Memory

Input-Output Interface

Flaxer Eli - Process Control

Ch 5 - 3

CPU - Memory - I/O

JZ

CPU Memory I/O Pripheral

A.B. D.B. RD WR CS A.B. D.B. RD WR CS A.B. D.B. RD WR MEM IO ROM RAM FLASH I/O Map Keyboard Printer More ... Mouse

Flaxer Eli - Process Control

Ch 5 - 4

Outline

General Architecture of Computer

– CPU - MEM - I/O – Peripheral

Memory Hierarchy

– Main Memory – Auxiliary Memory

Input-Output Interface

Flaxer Eli - Process Control

Ch 5 - 5

Memory Hierarchy

CPU Cache L1 Cache L2 Main Mem

I/O Boundary

Hard Disk Magnetic Media Magnetic Tapes Optical Media Floppy Disk

Register Inside CPU Static RAM DRAM, ROM, EPROM, FLASH IDE, SCSI ZIP, JAZ, LS-120 DAT, Analog CD-ROM, CDR, CDRW, DVD Zevel

Internal

  • r

External Bus I / O Mapping Devices

Flaxer Eli - Process Control

Ch 5 - 6

Main Memory

RAM (Random Access Memory): – Static => Flip Flop, Fast, Expensive, No Controller. – Dynamic => Mos Capacitor, Slow, Cheap, Refreshing controller. ROM (Read Only Memory): – Type: ROM, PROM, EPROM, E2PROM, Flash. – Used: BIOS, Table, etc. Not all the memory address space must be occupied,

parts of them can be empty (without memory or other devices).

slide-2
SLIDE 2

Flaxer Eli - Process Control

Ch 5 - 7

RAM & ROM Chips

RAM 2n x k

CS RD WR AB Chip Select Read Write n-Bit Address k-Bit Data Bus

ROM 2n x k

CS RD AB Chip Select Read n-Bit Address k-Bit Data Bus

Data Bus Function WR RD CS Tri -State None x x Tri -State None

1

From Outside Write 1

1

From Memory Read 1

1

Ilegal 1 1

1 Data Bus Function RD CS Tri -State None x Tri -State None 1 From Memory Read 1 1

Flaxer Eli - Process Control

Ch 5 - 8

Memory Address Map

RAM 0 1K x 8

CS RD WR AB

RAM 1 1K x 8

CS RD WR AB

RAM 2 1K x 8

CS RD WR AB

RAM 3 1K x 8

CS RD WR AB

ROM 4K x 8

CS RD AB

Decoder

1 2 3

CPU

AB(0..11) RD

AB(10..11)

AB(12) AB(0..9) AB(0..11) AB(13..15) WR

A 10 A 11 A 12 END BEGIN 03FFH 0000 H RAM 0 1 07FFH 0400 H RAM 1 1 0BFFH 0800 H RAM 2 1 1 0FFFH 0C00H RAM 3 x x 1 1FFFH 1000 H ROM

EN DB(0..7)

Flaxer Eli - Process Control

Ch 5 - 9

Address Map Table

A10 A11 A12 END BEGIN 03FFH 0000 H RAM 0 1 07FFH 0400 H RAM 1 1 0BFFH 0800 H RAM 2 1 1 0FFFH 0C00H RAM 3 x x 1 1FFFH 1000 H ROM

Flaxer Eli - Process Control

Ch 5 - 10

Unoccupied Memory Address

ROM 4K x 8

CS RD AB

A10 A11 A12 END BEGIN 03FFH 0000 H RAM 0 1 07FFH 0400 H RAM 1 1 0BFFH 0800 H None 1 1 0C03H 0C00H Reg x x 1 1FFFH 1000 H ROM

RAM 0 1K x 8

CS RD WR AB

RAM 1 1K x 8

CS RD WR AB

Decoder

1 2 3

CPU

AB(0..11) RD

AB(10..11)

AB(12) AB(0..9) AB(0..11) AB(13..15) WR EN DB(0..7)

Reg 4 x 8

CS RD WR AB AB(0..1)

Flaxer Eli - Process Control

Ch 5 - 11

Address Map Table

A10 A 11 A12 END BEGIN 03FFH 0000 H RAM 0 1 07FFH 0400 H RAM 1 1 0BFFH 0800 H None 1 1 0C03H 0C00H Reg x x 1 1FFFH 1000 H ROM

Flaxer Eli - Process Control

Ch 5 - 12

Auxiliary Memory

Hard Disk: – IDE => 30G, Fast, Internal. – Scsi => 100G, Ultra Fast, Internal / External. TAPE : – DAT: Slow, 100G per cassette. – Travan: Very Slow, 1G per cassette.

Optics:

– CD, CDR, CDRW => 640M. – DVD, DVD-RAM => 5G.

Removable:

– Zip => 100M, 250M. – Jaz => 1G, 2G. – Ls-120 => 120M.

– More => Floppy, Flash, ... .

slide-3
SLIDE 3

Flaxer Eli - Process Control

Ch 5 - 13

Outline

General Architecture of Computer

– CPU - MEM - I/O – Peripheral

Memory Hierarchy

– Main Memory – Auxiliary Memory

Input-Output Interface

Flaxer Eli - Process Control

Ch 5 - 14

Input-Output Interface

I/O interface provide a method for transferring

information between internal storage and external I/O devices.

To resolve the differences between CPU and

peripherals (Mechanism, Transfer Rate, Format, etc) the system include interface.

In addition, each device may have its own controller

that supervise the operation of the particular mechanism in the peripheral.

Flaxer Eli - Process Control

Ch 5 - 15

I/O Bus and Interface

CPU Interface Keyboard & Display Interface Printer Interface Hard Disk Interface CD

  • r

DVD

Data Bus Addr Bus Control

Flaxer Eli - Process Control

Ch 5 - 16

Input-Output Interface

To communicate with particular device, the processor

place a devise address on the address bus (Port Addr).

When the interface detects ins own address, it activates

the device that it controls. All others peripherals are disable in Tri-State.

At the same time the processor provides a function

code in the control lines.

The data send / received in Bi-directional data bus. Each CPU has special opcode for I/O operation.

Flaxer Eli - Process Control

Ch 5 - 17

Physical Memory Accessing

Assembler READ WRITE

Mov DI , AbsAdr Mov DI , AbsAdr Mov Al , [DI] Mov [DI] , Al

C & C++ READ WRITE

char *AbsAdrPtr = AbsAdr; MyData = (*AbsAdrPtr) ; (*AbsAdrPtr) = MyData;

Flaxer Eli - Process Control

Ch 5 - 18

Physical Memory Accessing

static unsigned char *kbf1; int pt1; int main () { unsigned char temp; MapPhysicalMemory (0x417, 1, &kbf1, &pt1); temp = *kbf1; printf(“%x”, temp); UnMapPhysicalMemory (pt1); }

  • If the operation system not allow direct accessing to the

hardware, we must use tool kit or lib to map the physical memory to the pointer.

  • Each compiler has it’s own library
slide-4
SLIDE 4

Flaxer Eli - Process Control

Ch 5 - 19

Physical Memory Accessing

int main () { unsigned char temp; ReadFromPhysicalMemory (0x417, temp, 1); WriteToPhysicalMemory (0x469, 1000, 4); printf(“%x”, temp); }

  • ReadFromPhysicalMemory (AbsAdr, Buffer, Number_Of_Byte);
  • WriteToPhysicalMemory (AbsAdr, Buffer, Number_Of_Byte);

Flaxer Eli - Process Control

Ch 5 - 20

Input-Output Instruction

Assembler IN OUT

BYTE In AL , Op1 Out Op1, AL WORD In AX , Op1 Out Op1, AX DWORD In EAX, Op1 Out Op1, EAX Op1 = Immd 8 bit Addr or 16 bit address in DX.

C & C++ IN OUT

BYTE char inp (int Address)

  • utp (int Address, char Data)

WORD short inpw (int Address)

  • utpw (int Address, short Data)

Flaxer Eli - Process Control

Ch 5 - 21

Input-Output Instruction

PASCAL & DELPHI 1.0

BYTE Data := Port[Address] Port[Address] := Data WORD Data := Portw[Address] Portw[Address] := Data

DELPHI 2.0+ (32 bit)

Not Support Not Support Use inline assembler Use inline assembler

BASIC

Data% = INP(Address%) OUT(Address%, Data%)

VISUAL BASIC

Not Support Not Support Use external DLL Use external DLL

Flaxer Eli - Process Control

Ch 5 - 22

Example: 8254

8254

CS RD WR

CPU

AB(2..9) IOR AB(1) IOW DB(0..7) DB A1 A0 AB(0)

Port Select

Timer 0 Timer 1 Timer 2 Status Control Base Port Address is: 0x40 Port Space is: 1024 ports

Flaxer Eli - Process Control

Ch 5 - 23

8254 Addresses

WR RD A 0 A 1 CS Select x x x x Tri -State x x 1 Timer 0 x x 1 1 Timer 1 x x 1 1 Timer 2 1 1 1 1 Control 1 1 1 1 Status

Flaxer Eli - Process Control

Ch 5 - 24

8254 Control

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

SC

Select Counter

RW Read / Write M

Mode

BCD

Bin / BCD

slide-5
SLIDE 5

Flaxer Eli - Process Control

Ch 5 - 25

8254 Control Field

SC1 SC0 Select Counter 1 Select Counter 1 1 Select Counter 2 1 1 Read - Back Command RW1 RW0 Counter Latch Command 1 Read / Write LSB 1 Read / Write MSB 1 1 Read / Write LSB first & MSB after SC - Select Counter RW - Read Write

Flaxer Eli - Process Control

Ch 5 - 26

8254 Control Field

M2 M1 M0 Mode 0 1 Mode 1 1 Mode 2 1 1 Mode 3 1 Mode 4 1 1 Mode 5 BCD Binary Counter 16 Bit 1 BCD Counter 4 Digit

M - Mode BCD - Binary Code Decimal

Flaxer Eli - Process Control

Ch 5 - 27

I/O Programming Example (C)

int main () { unsigned char temp; temp = 0xB6;

  • utp(0x43, temp)

// write control

  • utp(0x42, 0x34)

// write least

  • utp(0x42, 0x12)

// write most }

  • Set the Timer2 of 8254 to mode 3, Binary counting, and 16

bit interfacing. Load the counter with 0x1234.

1 1 1 1 1

= 0xB6

Flaxer Eli - Process Control

Ch 5 - 28

Shift Operations

  • C language has two shift operations for variable and constant:

>> (shift right) << (shift left).

  • Shift left operation always insert ‘0’ to the LSB

1 1 1 1

0x36=54

1 1 1 1

0x6C=108 after

Flaxer Eli - Process Control

Ch 5 - 29

Shift Operations

  • Shift right operation insert, to the MSB, value that depended

in the type of the variable or the constant.

  • If the type is unsigned, ‘0’ is insert to the MSB

1 1 1 1

0x36=54

1 1 1 1

0x1B=27 after

Flaxer Eli - Process Control

Ch 5 - 30

Shift Operations

1 1 1 1

0x36=54

1 1 1 1

0x1B=27 after

  • If the type is sign, the MSB is duplicated (sign extended).

1 1 1 1 1

0xB6=-74

1 1 1 1 1 1

0xDB=-37 after

slide-6
SLIDE 6

Flaxer Eli - Process Control

Ch 5 - 31

Shift Operations Example (C)

int main () { unsigned char x, y; char a, b; x = 1; // x = 00000001 y = x << 3; // y = 8 x = 255; // x = 11111111 y = x >> 3; // y = 31 a = 1; // a = 00000001 b = a << 3; // b = 8 a = -1; // a = 11111111 b = a >> 3; // b = -1 }

Flaxer Eli - Process Control

Ch 5 - 32

Constant Shift Operations

  • The shift operations work with a constant too.
  • For example:

–

1 << 3 = 8

–

48 >> 2 = 12

  • Constant integer, is by default 32 bit signed.
  • Unsigned constant is defined by U.

1 1 1

Flaxer Eli - Process Control

Ch 5 - 33

Bit Manipulations

  • How to set especial bit of the variable ?
  • Set the k bit:

–

x |= (1 << k)

– For example set bit 3 X |= (1 << 3):

1 1 1 1

1 << 3

1 1 1 1

X = 0x13 X = 0x1B

Flaxer Eli - Process Control

Ch 5 - 34

Bit Manipulations

  • How to clear especial bit of the variable ?
  • Clear the k bit:

–

x &= ~(1 << k)

– For example clear bit 3 X &= ~(1 << 3):

1 1 1 1 1 1 1 1 1 1 1 1 ~(1 << 3) 1 1 1 1

X = 0x7C X = 0x74

Flaxer Eli - Process Control

Ch 5 - 35

Bit Sensing

  • How to check especial bit of the variable ?
  • Check the k bit of variable Y:

– Y & (1 << k) – For example check bit 3 Y & (1 << 3):

1 x 1 1 1

1 << 3

x

If (x == 0) the all expression is FALSE If (x == 1) the all expression is TRUE

Y

Flaxer Eli - Process Control

Ch 5 - 36

Byte to Bit Conversion Example (C)

Void Byte2Bit (char b, char y[]) { int k; for (k=0; k<8; k++) y[k] = b & (1<<k); } Void Byte2Bit (char b, char y[]) { int k; for (k=0; k<8; k++, b >>= 1) y[k] = b & 1; }

slide-7
SLIDE 7

Flaxer Eli - Process Control

Ch 5 - 37

Bit to Byte Conversion Example (C)

char Bit2Byte (char y[]) { int k, b; for (k=0, b=0; k<8; k++) b |= (y[k] << k); return(b); } char Bit2Byte (char y[]) { int k, b; for (k=7, b=0; k>=0; b |= y[k--]) b <<= 1; return(b); }