Chapter 4 Basic Concepts in VHDL 1 benyamin@mehr.sharif.edu - - PowerPoint PPT Presentation

▶
chapter 4
SMART_READER_LITE
LIVE PREVIEW

Chapter 4 Basic Concepts in VHDL 1 benyamin@mehr.sharif.edu - - PowerPoint PPT Presentation

Apr 08, 2024 32 likes •517 views

Chapter 4 Basic Concepts in VHDL 1 benyamin@mehr.sharif.edu Characterizing Hardware Languages Timing a x a:=x; a<=x AFTER 10 ns; b Concurrency Adder R.F Ctrl 2 benyamin@mehr.sharif.edu Concurrency in VHDL VHDL

slide-1
SLIDE 1

1 benyamin@mehr.sharif.edu

Chapter 4

Basic Concepts in VHDL

slide-2
SLIDE 2

2 benyamin@mehr.sharif.edu

Characterizing Hardware Languages

  • Timing
  • Concurrency

a b x Adder Ctrl R.F a:=x; a<=x AFTER 10 ns;

slide-3
SLIDE 3

3 benyamin@mehr.sharif.edu

Concurrency in VHDL

  • VHDL concurrent body

ARCHITECTURE concurrent OF x IS … BEGIN signal assignment component instantiation assertion statement process statement END;

slide-4
SLIDE 4

4 benyamin@mehr.sharif.edu

Concurrency in VHDL

  • VHDL sequential body

ARCHITECTURE concurrent OF x IS … BEGIN process begin if statement while statement variable assignment end process; END; Concurrent Statement

slide-5
SLIDE 5

5 benyamin@mehr.sharif.edu

Concurrency and Timing Example

z c=1 w b=1 a (1->0) x y

g 1

g 2 g 3 g 4 Delay of each gate=12 ns g1 g2 g3 g4 0 12 24 36

Reacting Reacting Reacting Reacting Reacting

slide-6
SLIDE 6

6 benyamin@mehr.sharif.edu

Concurrency and Timing Example

z c=1 w b=1 a (1->0) x y

g 1

g 2 g 3 g 4 Delay of each gate=12 ns a b c w x y z 0 12 24 36

slide-7
SLIDE 7

7 benyamin@mehr.sharif.edu

Signal Declaration

  • Signals must be declared in declaration area of

architecture body

SIGNAL ID{,ID} : type := init_val ;

SIGNAL a : BIT :=‘1’; SIGNAL x,y,z : std_logic :=‘U’;

slide-8
SLIDE 8

8 benyamin@mehr.sharif.edu

Signal Assignment

  • Target1<=waveform AFTER 5 ns ;
  • Target1<=TRANSPORT waveform AFTER 5 ns ;
  • Target1<=REJECT 3 ns INERTIAL wvfrm AFTER 4 ns ;

AFTER Clause Inertial Delay Transport Delay

slide-9
SLIDE 9

9 benyamin@mehr.sharif.edu

Transport Delay

3 2 3

A B = 1 C

A C Delay = 2

C<= TRANSPORT A AND B AFTER 2 ns;

slide-10
SLIDE 10

10 benyamin@mehr.sharif.edu

Inertial Delay

R C

slide-11
SLIDE 11

11 benyamin@mehr.sharif.edu

Input Inertial Delay

3 2 3

A B = 1 C

A dI=4 C dI=2 C

C<=REJECT 4 ns INERTIAL A AND B AFTER 2 ns; C<=REJECT 2 ns INERTIAL A AND B AFTER 2 ns;

slide-12
SLIDE 12

12 benyamin@mehr.sharif.edu

Output Inertial Delay

2 2 2 3 1 2 3 3 A B C C A B A B C A B C

Delay=3

slide-13
SLIDE 13

13 benyamin@mehr.sharif.edu

Concurrent Assignments

ENTITY example IS PORT(a,b,c:IN BIT; z:OUT BIT); END; ARCHITECTURE concurrent OF example IS Signal w,x,y:BIT:=‘0’; BEGIN w<=NOT a AFTER 12 ns; x<=a AND b AFTER 12 ns; y<=c AND w AFTER 12 ns; z<=x OR y AFTER 12 ns; END;

z c w b a x y z Signal Declaration

slide-14
SLIDE 14

14 benyamin@mehr.sharif.edu

Signal Driver

…. t3 t2 t1 …. v3 v2 v1

now

v0 Driving value Signal

slide-15
SLIDE 15

15 benyamin@mehr.sharif.edu

Multiple Signal Assignment

…. t3 t2 t1 …. v3 v2 v1

now

v0 Driving value1 …. t’3 t’2 t’1 …. v’3 v’2 v’1

now

v’0 Driving value2

Resolution Function Signal Value a a<= waveform1; a<=waveform2;

slide-16
SLIDE 16

16 benyamin@mehr.sharif.edu

Events and Transactions

  • Event: when a waveform causes the value of

the target signal to change, an event is said to have occurred on the target signal.

  • Transaction: when a value is scheduled to be

assigned to a target signal after a given time, a transaction is said to have been placed on the driver of the target signal.

  • Transaction may cause an event or not.
slide-17
SLIDE 17

17 benyamin@mehr.sharif.edu

Transaction and Event in Signal Driver

…. t3 t2 t1 …. v3 v2 v1

now

v0 Driving value Signal

Transaction Event

slide-18
SLIDE 18

18 benyamin@mehr.sharif.edu

Event and Transaction Example

ARCHITECTURE demo OF example IS SIGNAL a,b,c:BIT:=‘0’; BEGIN a<=‘1’ AFTER 15 ns; b<= NOT a AFTER 5 ns; c<= a AFTER 10 ns; END;

a b c 0 5 10 15 20 25 30

slide-19
SLIDE 19

19 benyamin@mehr.sharif.edu

Transaction Placement and Expiration

a c b 0 5 10 15 20 25 ns

(1,15) a (1,5) b (0,10) c (1,5) b (0,10) c

0 5 10 15 20 25 ns c b

slide-20
SLIDE 20

20 benyamin@mehr.sharif.edu

Delta Delay

  • VHDL defines a simulation cycle as an

internal delay, referred to as δ delay.

  • It is used to model hardware concurrency.
  • Each concurrent statement in VHDL,

consumes 1δ delay to execute.

slide-21
SLIDE 21

21 benyamin@mehr.sharif.edu

δ Delay Demonstration

ARCHITECTURE delta OF timing IS SIGNAL a,b,c:BIT:=‘0’; BEGIN a<=‘1’; b<= NOT a; c<= NOT b; END;

b c 0 1 2 3 4 5 δ a

slide-22
SLIDE 22

22 benyamin@mehr.sharif.edu

δ Delay Demonstration

ARCHITECTURE delta OF timing IS SIGNAL a,b,c:BIT:=‘0’; BEGIN a<=‘1’ AFTER 5 NS; b<= NOT a; c<= NOT b AFTER 5 NS; END;

0 1δ 5 1δ 10 a c(1,5) is removed by c(0,5) b c

slide-23
SLIDE 23

23 benyamin@mehr.sharif.edu

δ Delay

y x Entity deltadelay is End; Architecture one of deltadelay is Signal y:bit:=‘1’; Signal x:bit:=‘0’; Begin x<=y; y<=not x; End; x y 0 1 2 3 4 5

slide-24
SLIDE 24

24 benyamin@mehr.sharif.edu

Sequential Placement of Transactions

begin Process Begin x<=v1 after t1; x<=v2 after t2; End process; End; Architecture a of b is begin x<=v1,v2 after t1; z<=x after t2; End;

Sequential Body Concurrent Body

slide-25
SLIDE 25

25 benyamin@mehr.sharif.edu

Sequential Placement of Transactions

Overwrite Append Append

Vnew /= Vexist tnew-texist <=reject Vnew /= Vexist tnew-texist >reject Vnew = Vexist

Overwrite Inertial Append Overwrite Transport tnew>texist tnew<=texist

slide-26
SLIDE 26

26 benyamin@mehr.sharif.edu

Sequential Placement - Discarding

ARCHITECTURE seq OF delay IS SIGNAL x:std_logic := ‘Z’; BEGIN PROCESS BEGIN x<=‘1’ AFTER 5 ns; x<=TRANSPORT ‘0’ AFTER 3 ns; WAIT; END PROCESS; END;

0 1 2 3 4 5 6 7 8 ns Z

slide-27
SLIDE 27

27 benyamin@mehr.sharif.edu

Sequential Placement - Appending

ARCHITECTURE seq OF delay IS SIGNAL x:std_logic := ‘Z’; BEGIN PROCESS BEGIN x<=‘1’ AFTER 5 ns; x<=TRANSPORT ‘0’ AFTER 8 ns; WAIT; END PROCESS; END;

0 1 2 3 4 5 6 7 8 9 10ns Z

slide-28
SLIDE 28

28 benyamin@mehr.sharif.edu

Sequential Placement - Appending

ARCHITECTURE seq OF delay IS SIGNAL x:std_logic := ‘Z’; BEGIN PROCESS BEGIN x<=‘1’ AFTER 5 ns; x<=REJECT 2 ns ‘0’ AFTER 8 ns; WAIT; END PROCESS; END;

Z 0 1 2 3 4 5 6 7 8 9 10ns

slide-29
SLIDE 29

29 benyamin@mehr.sharif.edu

Sequential Placement - Discarding

ARCHITECTURE seq OF delay IS SIGNAL x:std_logic := ‘Z’; BEGIN PROCESS BEGIN x<=‘1’ AFTER 5 ns; x<=REJECT 4 ns ‘0’ AFTER 8 ns; WAIT; END PROCESS; END;

Z 0 1 2 3 4 5 6 7 8 9 10ns

slide-30
SLIDE 30

30 benyamin@mehr.sharif.edu

Pulse Rejection

a<=‘0’ , ‘1’ after 5 ns ,’0’ after 20 ns,’1’ after 40 ns,’0’ after 45 ns;

x<= a after 10 ns;

15 5 a x

x<= REJECT 10 ns INERTIAL a after 10 ns;

slide-31
SLIDE 31

31 benyamin@mehr.sharif.edu

Structural Specification of Hardware

Chapter 5

slide-32
SLIDE 32

32 benyamin@mehr.sharif.edu

Structural Level

  • Components of the system are

listed and interconnections between them are specified (netlist)

slide-33
SLIDE 33

33 benyamin@mehr.sharif.edu

VHDL Language

  • 1. Selection of component from a certain

package or library

  • 2. Binding or association the usage of a

component to an available library

  • 3. Wiring mechanism
  • 4. Construction for specification of repetitive

hardware

slide-34
SLIDE 34

34 benyamin@mehr.sharif.edu

Parts Library - Inverter Model

Inv i1

  • 1

Entity inv IS PORT(i1:IN BIT;o1:OUT BIT); END inv; ARCHITECTURE single_delay OF inv IS BEGIN

  • 1<=NOT i1 AFTER 4 NS;

END; Inverter Symbol Inverter aspect notation

slide-35
SLIDE 35

35 benyamin@mehr.sharif.edu

Elements of Aspect Notation

entity_name Interface Aspect Input output port port Bidirectional Buffer port port

slide-36
SLIDE 36

36 benyamin@mehr.sharif.edu

Details of The Entity

ENTITY inv IS PORT ( i1: IN BIT ;

  • 1:OUT BIT

) ; END inv;

Interface signal declaration Interface signal declaration port clause Entity declaration

slide-37
SLIDE 37

37 benyamin@mehr.sharif.edu

Parts Library - Nand2 Gate Model

Entity nand2 IS PORT(i1,i2:IN BIT; o1:OUT BIT); End; ARCHITECTURE single_delay OF nand2 IS BEGIN

  • 1<=i1 NAND i2 AFTER 5 ns;

END; Nand2

slide-38
SLIDE 38

38 benyamin@mehr.sharif.edu

Details of The Entity

ENTITY nand2 IS PORT ( i1 , i2 : IN BIT ;

  • 1:OUT BIT

) ; END;

Interface signal declaration port clause Entity declaration Identifier list mode type

slide-39
SLIDE 39

39 benyamin@mehr.sharif.edu

Parts Library - Nand3 Gate Model

Entity nand3 IS PORT(i1,i2,i3:IN BIT; o1:OUT BIT); End; ARCHITECTURE single_delay OF nand3 IS BEGIN

  • 1<=NOT(i1 AND i2 AND i3) AFTER 6 ns;

END; Nand2

slide-40
SLIDE 40

40 benyamin@mehr.sharif.edu

Wiring of Primitives – Comparator Design

A B > = < A>B A=B A<B

a_gt_b= a.gt+b’gt+a.b’ a_eq_b=a.b.eq+a’.b’.eq a_lt_b=a’.lt+b.lt+a’.b

slide-41
SLIDE 41

41 benyamin@mehr.sharif.edu

Comparator Design – Karnaugh Table

1 1 00 1 1 1 10 01 11

ab

< 1 1 00 1 1 1 10 01 11

ab

> 1 00 1 1 10 01 11

ab

=

slide-42
SLIDE 42

42 benyamin@mehr.sharif.edu

Comparator Design – Entity Declaration

Entity bit_comprator IS PORT( a,b, --data inputs gt, --previous greater than eq, -- previous equal lt:IN BIT; -- previous less than a_gt_b, -- greater than a_eq_b, --equal a_lt_b: OUT BIT --less than ); END;

  • - Comments
slide-43
SLIDE 43

43 benyamin@mehr.sharif.edu

Comparator Design – Architecture

Architecture gate_level OF bit_comparator IS

COMPONENT n1 IS PORT(i1:IN BIT;o1:OUT BIT);END COMPONENT; COMPONENT n2 is PORT(i1,i2:IN BIT;o1:OUT BIT);END COMPONENT; COMPONENT n3 is PORT(i1,i2,i3:IN BIT;o1:OUT BIT);END COMPONENT; FOR g0,g1:n1 USE ENTITY WORK.inv(single_delay); FOR ALL:n2 USE ENTITY WORK.nand2(single_delay); USE FOR ALL:n3 ENTITY WORK.nand3(single_delay); SIGNAL im1,im2,im3,im4,im5,im6,im7,im8,im9,im10: BIT; BEGIN g0: n1 PORT MAP(a,im1); g1: n1 PORT MAP(b,im2); g2: n2 PORT MAP(a,im2,im3); g3: n2 PORT MAP(a,gt,im4); g4: n2 PORT MAP(im2,gt,im5); g5: n3 PORT MAP(im3,im4,im5,a_gt_b); g6: n3 PORT MAP(im1,im2,eq,im6); g7: n3 PORT MAP(a,b,eq,im7); g8: n2 PORT MAP(im6,im7,a_eq_b); g9: n2 PORT MAP(im1,b,im8); g10: n2 PORT MAP(im1,lt,im9); g11: n2 PORT MAP(b,lt,im10); g12: n3 PORT MAP(im8,im9,im10,a_lt_b); END;

Binding Component Declaration Netlist Wiring

slide-44
SLIDE 44

44 benyamin@mehr.sharif.edu

Component Declaration - VHDL87

COMPONENT comp_name IS port_declaration END COMPONENT;

COMPONENT n2 IS PORT(i1,i2:IN BIT;o1:OUT BIT); END COMPONENT;

slide-45
SLIDE 45

45 benyamin@mehr.sharif.edu

Configuration Specification VHDL87

FOR lables : compe_name USE ENTITY Library.EntityName(ArchName); FOR ALL:n1 USE ENTITY WORK.inv(single_delay); FOR g0,g1:n1 USE ENTITY WORK.inv(single_delay);

slide-46
SLIDE 46

46 benyamin@mehr.sharif.edu

Component Instantiation - VHDL87

lable: comp_name [GENERIC MAP(association_list)] PORT MAP(association_list); g2 : n2 PORT MAP(a,im2,im3);

Component Lable Component Name Port Map Aspect Association Lsit

slide-47
SLIDE 47

47 benyamin@mehr.sharif.edu

Component Instantiation VHDL93

lable: ENTITY LibraryName.comp_name[(ArchName)] [GENERIC MAP(association_list)] PORT MAP(association_list);

g0:ENTITY WORK.inv(single_delay) PORT MAP(a,abar);

  • Component_Declaration is eliminated
  • Configuration_Specification is eliminated
slide-48
SLIDE 48

48 benyamin@mehr.sharif.edu

Comparator Design – VHDL93

Architecture gate_level OF bit_comparator IS

SIGNAL im1,im2,im3,im4,im5,im6,im7,im8,im9,im10: BIT; BEGIN g0: entity work.inv(single_delay) PORT MAP(a,im1); g1: entity work.inv PORT MAP(b,im2); g2: entity work.nand2 PORT MAP(a,im2,im3); g3: entity work.nand2 PORT MAP(a,gt,im4); g4: entity work.nand2 PORT MAP(im2,gt,im5); g5: entity work.nand3 PORT MAP(im3,im4,im5,a_gt_b); g6: entity work.nand3 PORT MAP(im1,im2,eq,im6); g7: entity work.nand3 PORT MAP(a,b,eq,im7); g8: entity work.nand2 PORT MAP(im6,im7,a_eq_b); g9: entity work.nand2 PORT MAP(im1,b,im8); g10: entity work.nand2 PORT MAP(im1,lt,im9); g11: entity work.nand2 PORT MAP(b,lt,im10); g12: entity work.nand3 PORT MAP(im8,im9,im10,a_lt_b); END;