Chapter 3-7 2, find the corresponding domino gate using a PDN net - - PowerPoint PPT Presentation

SLIDE 1

1

Digital IC-Design

Chapter 3-7 An Exercise

1, draw the static transistor schematic for the function f = (A+BC)D

Problem

Parameters from a 0.35 um process 2, find the corresponding domino gate using a PDN net 3, find the Euler path for the PDN and draw the layout 4, calculate the parasitic capacitances for the PDN. Assume that the circuit is precharged to VDD=3V. Neglect the wire it capacitances 5, determine the output voltage in the evaluation phase. Assume worst case charge sharing between the precharged node and the internal nodes in the PDN 6, suggest a solution to the charge sharing problem 7 calculate the t in the precharged node when all input

Problem

Parameters from a 0.35 um process 7, calculate the tpLH in the precharged node when all input signals are low during precharge. Use the physical model first and compare the result with the equivalent resistor model for the transistor 8, determine the power-delay product for the first stage. Determine the power consumption if the operating frequency is 500 MH 500 MHz 9, determine the threshold point VM for the inverter stage

1, draw the static transistor schematic for the function Q = (A+BC)D

Problem 1

The function is non-inverting, i.e. a two stage operation. Make the inverse function of Q followed by an inverter. The PDN for the first stage is . B and C are placed in series and both are in parallel with A. D is placed in series with the other.

( ) Q A BC D = +

The PUN is found by De Morgan law’s or by duality i.e. serial connections in PDN corresponds to parallel in the PUN and vice versa.

SLIDE 2

2

1, draw the static transistor schematic for the function Q = (A+BC)D

Static Gate

C B f(A+BC)D B A C B D A C D

Domino Logic

2, find the corresponding domino gate using a PDN net

φ

PDN

φ

2, find the corresponding domino gate using a PDN net

Domino Logic

VDD

A C B f(A+BC)D

φ

A C B D f(A+BC)D A C B D

VDD

D

φ

Static gate

3, find the Euler path for the PDN and draw the layout

Euler Path

VDD

A C B f(A+BC)D

φ

D

φ

SLIDE 3

3

3, find the Euler path for the PDN and draw the layout

Euler Path and Layout

φ

VDD

Euler Path

A C B D

φ

f(A+BC)D

DD

V

f

GND

A C B D φ

Note: the path goes through the ground

4, calculate the parasitic capacitances in the PDN. Assume that the circuit is precharged to VDD = 3V. Neglect the wire capacitances.

Parasitic Capacitances

A C B f(A+BC)D

φ

VDD

VDD

f

C1 C3 C2 C1 0V 3V

D

φ GND

A C B D φ

C3 C2 C4=C3

C1 Capacitance

4, calculate the parasitic capacitances in the PDN.

C1 consists of: Overlap C in the A, B,

VDD

p , , and Φ p-transistor Diffusion C in n- and p- drain areas Channel & Overlap C in

φ

f C1 Channel & Overlap C in the inverter Wire C is neglected

GND

A C B D φ

Overlap Capacitance

Drain Source Gate

L W

CGD = Co × W CGS = Co × W

CGS CGD CGC

L W

C0 is a constant per unit length C0 in fF/um2

SLIDE 4

4

The Miller Effect If Cgd is modeled from Vout to GND, the value shall be doubled the value shall be doubled

Cgd

V Δ ΔV

2C d

V Δ ΔV

2Cgd

Cgd = 2 C0 W

Parameters – 0.35um

Capacitances Cox 4.6 fF/mm2 C0 (C d C ) 0 21 fF/mm Electrical Parameters kn’ 175 mA/V2 VTn 0.5 V C0 (Cgd0 Cgs0) 0.21 fF/mm Cj0n 0.93 fF/mm2 Cj0p 1.42 fF/mm2 Cjsw0n 0.28 fF/mm Cjsw0p 0.38 fF/mm

Tn

L (0.35mm) 0.3 mm W (0.6mm) 0.55 mm γn 0.58 V1/2 λn 0.05 1/V kp’

• 60

mA/V2 V 0 6 V VTp

• 0.6

V L (0.35mm) 0.38 mm W (0.6mm) 0.55 mm γp

• 0.5

V1/2 λp

• 0.15

1/V Velocity Saturation VDSATn 0.82 V VDSATp

• 1.3

V

Overlap Cap. Cgd

4, calculate the parasitic capacitances in the PDN.

GND -> VDD/2 or VDD -> VDD/2 transition is assumed (to 50% point)

VDD

f

C1 CGD

2 3 ( ) 6(0.21 1.0 ) 1 26

gd

C C W fF m m fF μ μ = × × × = = × =

GND

A C B D φ

1.26 fF =

Junction Capacitance

CDiff =CBot+CSW Drain/Source Diffusion

Bottom

CDiff CBot+CSW

Don’t count the wall towards the channel

T

• w

a r d s a n n e l

Bottom

G a t e T C h a n

Side Wall

W Ls

SLIDE 5

5

DBn eqn n j eqswn n jsw

C K AD C K PD C = × + ×

4, calculate the parasitic capacitances in the PDN.

Junction Capacitance

VDD

f

CDBp

Determine Keq (see eq 5.14)

( )

1 1

( ) ( ) ( )(1 )

m m m High Low eq High Low

V V K V V m φ φ φ

− −

− − − − = − −

GND

A C B D φ f

CDBn

Transition to 50% point Note: Reverse biased voltages (diodes) i.e. negative voltages

High-to-low transition (–VDD to –VDD/2) NMOS, Bottom plate

Determine Keq: Example ( )

1 1

0.5; 0.9 V; 3 V; 1.5 V ( ) ( ) ( )(1 )

High Low m m m High Low eq Hi h L

m V V V V K V V m φ φ φ φ

− −

= = = − = − − − − − = = − −

( )

0.5 1 0.5 1 0.5

( )(1 ) 0.9 (0.9 3) (0.9 1.5) ( 3 1.5)(1 0.5) 0.54

High Low

V V m

− −

− + − + = = − + − =

Determine Keq

NMOS, 0.35 um technology, VDD=3 V

High-to-low Bottom plate Keqn=0.54 g p

eqn

High-to-low Sidewall Keqswn=0.58 Low-to-high Bottom plate Keqn=0.76 Low-to-high Sidewall Keqswn=0.78

PMOS, 0.35 um technology, VDD=3 V

High-to-low Bottom plate Keqp=0.77 High-to-low Sidewall Keqswp=0.84 Low-to-high Bottom plate Keqp=0.55 Low-to-high Sidewall Keqswp=0.67

4, calculate the parasitic capacitances in the PDN.

NMOS If high-to-low transition:

Junction Capacitance

VDD

f

C1 Cj 0.54 1 1 0.93 0.58 2 1 0.28 0.83

DBn eqn n j n eqswn n jsw n

C K AD C K PD C fF = × + × = = × × × + × × × =

GND

A C B D φ f

1

Area 1um2 Sidewall 2um

SLIDE 6

6

4, calculate the parasitic capacitances in the PDN.

PMOS If high-to-low transition:

A 1

2

Junction Capacitance

VDD

f

C1 Cj Area 1um2 Sidewall 3um 0.77 1 1 1.42 0.84 3 1 0.38 2.01

DBp eqp n j p eqswp p jsw p

C K AD C K PD C fF = × + × = = × × × + × × × =

GND

A C B D φ f

1

Channel Capacitance

Drain Source Gate

L W

CGC can be:

CGS CGD CGC

CGC can be:

CGCB = Gate cap. to bulk CGCD = Gate cap. to drain CGCS = Gate cap. to source Dependent on oxide capacitance and area COX (F/μm2) LW (μm2)

Cut off Linear

Channel Capacitance

n+ n+ n+ n+

Saturation GCB

C

n+ n+

GCS GCD

C C Gate-Channel Capacitance

(Table 3-4) To Bulk To Source To Drain Total Gate Cap.

CGCB CGCS CGCD CG Cut off: No channel ⇒ CGC = CGCB

Cutoff COX W L COX W L + 2 C0W Resistive (1/2) COX W L (1/2) COX W L COX W L + 2 C0W Saturation (2/3) COX W L (2/3) COX W L + 2 C0W

Resistive: Channel ⇒ Divide CGC in two parts Saturation: ≈ 2/3 of Channel to source

SLIDE 7

7

Total Gate Cap. CGn

2 2 3 2

Gn GS GD GC OX

C C C C C W C W L = + + = × + × × =

4, calculate the parasitic capacitances in the PDN.

2 2 0.21 1 4.6 1.0 0.3 3 1.34 fF = × × + × × = =

VDD

f

C1 CGn High-to-low transition => CGn is in Saturation and is closing GND

A C B D φ

1.0 um

Total Gate Cap. CGp

2

Gp GS GD GC OX

C C C C C W C W L = + + = × + × × =

4, calculate the parasitic capacitances in the PDN.

CGp

2 0.21 1 4.6 1.0 0.38 2.17 fF = × × + × × = =

VDD

f

C1 1.0 um GND

A C B D φ

High-to-low transition => CGp is in Cutoff and is opening

C1 Capacitance

1 G G G

C C C C C C = + + + + + =

4, calculate the parasitic capacitances in the PDN.

Total Cap in node C1

1

1.26 0.83 2.01 1.34 2.17 7.61

GD DBn DBp Gn Gp

C C C C C C fF + + + + + = + + + + = =

VDD

f C1

GND

A C B D φ

C2

VDD 4, calculate the parasitic capacitances in the PDN. 2 /

2 3

GD GS DBn

C C C C W = + = = × × × +

G

A C B D φ f

C1 C2

2 3 0.21 1 2 0 54 1 1 0 93

eqn n j n eqswn n jsw n

K AD C K PD C + × + + × = = × × × + + × × × × +

GND

A C B D φ

2 0.54 1 1 0.93 0.58 5 1 0.28 3.08 fF + × × × × + + × × × =

SLIDE 8

8

C3

VDD 4, calculate the parasitic capacitances in the PDN. 3 /

2 2

GD GS DBn

C C C C W = + = = × × × +

G

A C B D φ f

C1 C2

2 2 2 2 0.21 1

eqn n j n eqswn n jsw n

C W K AD C K PD C × × × + + × + + × = = × × × +

GND

A C B D φ

C3

0.54 0.7 0.93 0.58 1.4 0.28 1.42 fF + × × + + × × =

Area 0.7um2 Sidewall 1.4um

5, calculate the output voltage in the evaluation phase. Assume worst case charge sharing between the precharged node and the internal nodes in the PDN

Charge Sharing

V

CL CA VDD VA

tot

• ut

tot tot L DD A A tot L A L DD A A

Q V C Q C V C V C C C C V C V V = = + = + +

fNAND

A->1 B=0

VDD

φ

CL CA CL CA Vout

• ut

L A A DD L

• ut

DD L A

V C C V V C V V C C = + << = +

φ

5, calculate the output voltage in the evaluation phase. Assume worst case charge sharing between the precharged node and the internal nodes in the PDN

Charge Sharing

7 61 C fF

Worst case when D-transistor off and when the C2 and C3 nodes are uncharged A C B f(A+BC)D

φ

VDD

C1 C3 C2 0V 3V

1 2 3

7.61 3.08 1.42 C fF C fF C fF = = =

1 1 C DD

C V V C C C = = + +

D

φ

1 2 3

7.61 3 1.89 V 7.61 3.08 1.42 C C C + + = × = + +

63 % of VDD

6, suggest a solution to the charge sharing problem

Charge Sharing

A C B D f(A+BC)D

φ

VDD

φ

A C B D f(A+BC)D

φ

VDD

Weak

φ φ

SLIDE 9

9

Propagation Delay

( ) C V V CV

7, calculate the tpLH in the precharged node when all input signals are low during precharge. Use the physical model first and compare the result with the equivalent resistor model for the transistor

Long Channel Model

1 1 2 2 1 1 2

(

• )

2 2 (

• )

(

• )

2 2

OH OL DD p p GS Tp pLH DD Tp pLH DD pLH

C V V CV Q C U k k Q I t V V t V V t CV C t = ×Δ = = = × = × = × = ≈

A B f(A+BC)D

φ

V DD

C1

2

(

• )

pLH p DD Tp p DD

t k V V k V

Ideal step on clock φ

A C D

φ

7, calculate the tpLH in the precharged node when all input signals are low during precharge. Use the physical model first and compare the result with the equivalent resistor model for the transistor

C C

Propagation Delay

Long Channel Modell

A B f(A+BC)D

φ

VDD

C1 Precharged to 3V

1 1 '

• 15
• 6

1

( ) ( ) 7.61 10 16 1.0 60 10 ( 3) 0.38

pLH p DD p DD DD

C C t W k V k V L ps CV = = = − − × = = − × × × −

C D

φ

1 ' 2

• 15
• 6

2

( ) 7.61 10 ( 3) 25 1.0 60 10 ( 3 ( 0.6)) 0.38

DD pLH p DD Tp

CV t W k V V L ps = = − × × − = = − × × × − − −

Propagation delay (page 202)

3 0.69 4

L DD pLH

C V t I = =

Short Channel Transistor

' 15

4 0.52 ( ) 2 7.61 10 ( 3) 0.52 33 1 1 3

DSAT L DD DSATp p DSATp DD Tp

I C V V W k V V V L ps

−

= = − − × × − = =

6

1 1.3 60 10 ( 1.3) ( 3 ( 0.6) ) 0.38 2

−

− − × × − × − − − −

Equivalent Resistance

(mA)

D

I

/ 2 DVDD

I

DVDD

I

( ) ( / 2) V V V V

R R +

(V)

DS

V ( ) ( / 2) ( ) ( / 2)

2 2

OUT DD OUT DD OUT DD OUT DD

V V V V eq DS DS D D V V V V eq

R R R V V I I R

= = = =

+ = = ⎡ ⎤ ⎡ ⎤ + ⎢ ⎥ ⎢ ⎥ ⎣ ⎦ ⎣ ⎦ =

SLIDE 10

10

Resistance in The PMOS Transistor

Long or Short Channel?

• 3
• 2
• 1
• 0.2
• 0.4

VDS (V) If VDSAT = -1.3 V ID (mA)

• 0.6
• 0.8

VGS =3 V

Long Channel

Resistance in the PMOS Transistor

I = - 0 61 mA ID = - 0.84 mA

3 1.5 0.84 0.61 2

eq p

R

−

− − + − − = =

• 3
• 2
• 1
• 0.2
• 0.4

VDS (V)

L ID = - 0.61 mA

3.0 k = Ω

ID (mA)

• 0.6
• 0.8

VGS =3 V

Long Channel

Resistance in The PMOS Transistor

I = 0 56 mA ID = 0.66 mA

3 1.5 0.66 0.56 2

eq p

R

−

− − + − − = =

• 2
• 1
• 0.2
• 0.4

VDS (V)

Sh ID = 0.56 mA

3.6 k = Ω

ID (mA)

• 0.6
• 0.8

VGS =3 V

Short Channel

Equivalent Resistance (Equation 3.43)

2 '

3 5 1 4 6 ( )

DSAT

DD eq p DD

V R V V W k V V V λ ⎛ ⎞ = − = ⎜ ⎟ ⎛ ⎞ ⎝ ⎠ ⎜ ⎟

2 6

( ) 2 3 3 5 1 ( 0.15) ( 3) 4 6 1.0 ( 1.3) 60 10 ( 3 ( 0.6)) (1.3) 0.38 2 3 9

DSATp

p DD Tp DSATp

W k V V V L k

−

− − ⎜ ⎟ ⎜ ⎟ ⎝ ⎠ − ⎛ ⎞ − × − × − = ⎜ ⎟ ⎛ ⎞ − ⎝ ⎠ − × × × − − − ×− − ⎜ ⎟ ⎝ ⎠ = Ω 3.9 k = Ω

Short Channel

SLIDE 11

11

7, calculate the tpLH in the precharged node when all input signals are low during precharge. Use the physical model first and compare the result with the equivalent resistor model for the transistor

Propagation Delay

B f(A+BC)D

φ

VDD

C1

1 3

• 15

0.69 0.69 3.9 10 7.61 10 20

pLH eq p

t R C ps

−

= × × = × × × × =

A C B D

φ 7, calculate the tpLH in the precharged node when all input signals are low during precharge. Use the physical model first and compare the result with the equivalent resistor model for the transistor

Propagation Delay

1

16

pLH p DD

C t ps k V CV = =

• 1

0.69 20

pLH eq p

t R C ps = × =

1 ' 2

25 (

• )

DD pLH p DD Tp

CV t ps W k V V L = =

Simulation: 17

pLH

t ps =

8, Calculate the power delay product for the first stage. Determine the power consumption if the operating frequency is 500 MHz.

Power Delay Product & Power Consump.

2 15 2 1

7.61 10 3 34 2 2

DD

CV PDP fJ

−

× × = = = Power Delay Product: Energy consumed per switching event Power Consumption

2 15 2 6 1

7.61 10 3 500 10 34

DD

P CV f W μ

−

= = × × × × =

9, determine the threshold point VM for the inverter stage

Threshold point VM

Long Channel

' '

1.0 ( 60) 0.35 0.586 1.0 175 0.35

p p p p n n n n

W k k L r W k k L − × − − × − = = = = × × ( ) 0.586 (3 ( 0.6)) 0.5 1.20 1 1 0.586

DD Tp Tn M

r V V V V V r × + + × + − + = = = + +

SLIDE 12

12

9, determine the threshold point VM for the inverter stage

Threshold point VM

Short Channel Both Velocity saturated

2 2

(( ) ) (( ) ) 2 2 Solving yields

DSATp DSATn n M Tn DSATn p DD M Tp DSATp M

V V k V V V k V V V V V − − = − + +

y

2 2 where 1

DSATp DSATn Tn DD Tp p DSATp M n DSATn

V V V r V V k V V r r k V ⎛ ⎞ + + + + ⎜ ⎟ ⎝ ⎠ = = +

9, determine the threshold point VM for the inverter stage

Threshold point VM

Short Channel

60 ( 1.3) 0.543 175 0.82 2 2

p DSATp n DSATn DSATp DSATn Tn DD Tp M

k V r k V V V V r V V V − − × − = = = × ⎛ ⎞ + + + + ⎜ ⎟ ⎝ ⎠ = = 1 0.82 1.3 0.5 0.543 3 ( 0.6) 2 2 1.21 1 0.543

M

r V + − ⎛ ⎞ + + + − + ⎜ ⎟ ⎝ ⎠ = = +