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Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/
Chapter 1 Professor Brendan Morris, SEB 3216, - - PowerPoint PPT Presentation
Chapter 1 Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/ CPE100: Digital Logic Design I Section 1004: Dr. Morris From Zero to One Chapter 1 <1> Background: Digital Logic Design
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Professor Brendan Morris, SEB 3216, brendan.morris@unlv.edu http://www.ee.unlv.edu/~b1morris/cpe100/
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focus of this course programs device drivers instructions registers datapaths controllers adders memories AND gates NOT gates amplifiers filters transistors diodes electrons
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1’s Column 10’s Column 100’s Column 1000’s Column
Five Thousand Three Hundred Seven Tens Four Ones Base 10
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1’s Column 2’s Column 4’s Column 8’s Column
One Eight One Four Zero Two One One Base 2
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least significant bit most significant bit
nibble byte
least significant byte most significant byte
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LSB MSB
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Hex Digit Decimal Equivalent Binary Equivalent 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 A 10 B 11 C 12 D 13 E 14 F 15
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Hex Digit Decimal Equivalent Binary Equivalent 0000 1 1 0001 2 2 0010 3 3 0011 4 4 0100 5 5 0101 6 6 0110 7 7 0111 8 8 1000 9 9 1001 A 10 1010 B 11 1011 C 12 1100 D 13 1101 E 14 1110 F 15 1111
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Octal Digit Decimal Equivalent Binary Equivalent 000 1 1 001 2 2 010 3 3 011 4 4 100 5 5 101 6 6 110 7 7 111
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≈ 1000 (1024)
≈ 1 billion (1,073,741,824)
≈ 1 trillion (1,099,511,627,776)
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≈ 1000 (1024)
≈ 1 billion (1,073,741,824)
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Decimal # 8-4-2-1 (BCD) 6-3-1-1 Excess-3 2-out-of-5 Gray 0000 0000 0011 00011 0000 1 0001 0001 0100 00101 0001 2 0010 0011 0101 00110 0011 3 0011 0100 0110 01001 0010 4 0100 0101 0111 01010 0110 5 0101 0111 1000 01100 1110 6 0110 1000 1001 10001 1010 7 0111 1001 1010 10010 1011 8 1000 1011 1011 10100 1001 9 1001 1100 1100 11000 1000
Each code combination represents a single decimal digit.
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Decimal # 8-4-2-1 (BCD) 6-3-1-1 0000 0000 1 0001 0001 2 0010 0011 3 0011 0100 4 0100 0101 5 0101 0111 6 0110 1000 7 0111 1001 8 1000 1011 9 1001 1100
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10002
Decimal # Excess-3 0011 1 0100 2 0101 3 0110 4 0111 5 1000 6 1001 7 1010 8 1011 9 1100
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Decimal # 2-out-of-5 00011 1 00101 2 00110 3 01001 4 01010 5 01100 6 10001 7 10010 8 10100 9 11000
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Decimal # Gray 0000 1 0001 2 0011 3 0010 4 0110 5 1110 6 1010 7 1011 8 1001 9 1000
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– Positive number: sign bit = 0 – Negative number: sign bit = 1
1
1 2 2 1 2
n
N N n a i i i
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– Positive number: sign bit = 0 – Negative number: sign bit = 1
1
1 2 2 1 2
n
N N n a i i i
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2 1 1
n n i n i i
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2 1 1
n n i n i i
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1000 1001
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
Two's Complement
1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
Sign/Magnitude Unsigned
Unsigned [0, 2N-1] Sign/Magnitude [-(2N-1-1), 2N-1-1] Two’s Complement [-2N-1, 2N-1-1]
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Y = AB A B Y 1 1 1 1 A B Y
Y = A + B A B Y 1 1 1 1 A B Y
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Y = AB A B Y 1 1 1 1 1 A B Y
Y = A + B A B Y 1 1 1 1 1 1 1 A B Y
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Y = A + B A B Y 1 1 1 1 A B Y
Y = A + B Y = AB Y = A + B A B Y 1 1 1 1 A B Y 1 1 1 1 A B Y 1 1 1 1 A B Y A B Y A B Y
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Y = A + B A B Y 1 1 1 1 A B Y
Y = A + B Y = AB Y = A + B A B Y 1 1 1 1 1 1 A B Y 1 1 1 1 1 1 1 A B Y 1 1 1 1 1 A B Y A B Y A B Y 1 1
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Y = A+B+C B C Y 1 1 1 1 A B Y C A 1 1 1 1 1 1 1 1
Y = ABC
A B
Y
C
B C Y 1 1 1 1 A 1 1 1 1 1 1 1 1
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Y = ABC
A B
Y
C
B C Y 1 1 1 1 A 1 1 1 1 1 1 1 1 1
Y = A+B+C B C Y 1 1 1 1 A B Y C A 1 1 1 1 1 1 1 1 1
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Driver Receiver Noise 5 V 4.5 V
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Driver Receiver
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Driver Receiver Forbidden Zone NML NMH Input Characteristics Output Characteristics VO H VDD VO L GND VIH VIL Logic High Input Range Logic Low Input Range Logic High Output Range Logic Low Output Range
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Forbidden Zone NML NMH Input Characteristics Output Characteristics VO H VDD VO L GND VIH VIL Logic High Input Range Logic Low Input Range Logic High Output Range Logic Low Output Range Driver Receiver
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g s d g = 0 s d g = 1 s d OFF ON
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Silicon Lattice Si Si Si Si Si Si Si Si Si As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si
+
Free hole n-Type p-Type
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n p gate source drain substrate SiO2 nMOS Polysilicon n gate source drain
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n p gate source drain substrate n n p gate source drain substrate n GND GND VDD GND +++++++
channel
Diode connection from p to n doped area current cannot travel from np
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SiO2 n gate source drain Polysilicon p p gate source drain substrate
Note bubble on gate to indicate on when low
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g s d g = 0 s d g = 1 s d g d s d s d s nMOS pMOS OFF ON ON OFF
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pMOS pull-up network
inputs
nMOS pull-down network
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𝐸𝐸
pMOS pull-up network
inputs
nMOS pull-down network
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Y = A A Y 1 1 A Y
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Y = A A Y 1 1 A Y
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NAND
Y = AB A B Y 1 1 1 1 1 1 1 A B Y
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NAND
Y = AB A B Y 1 1 1 1 1 1 1 A B Y
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Only high output when all three pMOS in series are “on” and create a path from output to 𝑊
𝐸𝐸
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Note: AND requires 2 more gates than NAND. Inverted logic is more efficient implementation.
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nMOS pull-down network weak
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GPUs
would today cost $100, get one million miles to the gallon, and explode once a year . . .” – Robert Cringley
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𝐸𝐸 is 𝐷𝑊 𝐸𝐸 2
𝐸𝐸 2 𝑔
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𝐸𝐸
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2 𝑔 + 𝐽𝐸𝐸𝑊𝐸𝐸