CENG5030 Part 1-2: Voltage Scaling —- A Dynamic Programming Approach Bei Yu (Latest update: January 14, 2019) Spring 2019 1 / 27
Overview Introduction Background: NP problem Background: Dynamic Programming DAC’07: Voltage Partitioning ICCAD’06: Voltage Assignment on Netlist ICCAD’07: Voltage Assignment on Slicing Floorplanning 2 / 27
Overview Introduction Background: NP problem Background: Dynamic Programming DAC’07: Voltage Partitioning ICCAD’06: Voltage Assignment on Netlist ICCAD’07: Voltage Assignment on Slicing Floorplanning 3 / 27
Multi-Voltage Design @IBM 1 1 Ruchir Puri et al. (2003). “Pushing ASIC performance in a power envelope”. In: Proc. DAC , pp. 788–793. 3 / 27
Level-Converter 2 Level-converter is used to avoid excessive static power consumption between the low and high voltage regions. 2 Ruchir Puri et al. (2003). “Pushing ASIC performance in a power envelope”. In: Proc. DAC , pp. 788–793. 4 / 27
Placement Level Multi-Voltage 3 3 Huaizhi Wu and Martin DF Wong (2009). “Incremental improvement of voltage assignment”. In: IEEE TCAD 28.2, pp. 217–230. 5 / 27
4 4 Kristof Blutman et al. (2017). “Floorplan and placement methodology for improved energy reduction in stacked power-domain design”. In: Proc. ASPDAC , pp. 444–449. 6 / 27
Floorplanning Level Multi-Voltage 8 2 Low voltage 6 ◮ Modules are assigned high-voltage or High voltage 7 4 low-voltage. ◮ Low voltage → high delay. 5 ◮ Trade off between the power saving and 1 3 performance. Power (d1,p1) (d2,p2) Delay 7 / 27
Floorplanning Level Multi-Voltage 8 2 Low voltage ◮ Modules are assigned high-voltage or 6 High voltage 7 low-voltage. 4 ◮ Low voltage → high delay. 5 ◮ Trade off between the power saving and 1 3 performance. ◮ Consider Power Network Resource ◮ High voltage modules should pack close ◮ Generate Voltage Island Power Network Resource 7 / 27
What’s Netlist? 1 2 3 5 4 6 N-1 N 2 Tcycle 5 N-1 1 4 N 3 8 / 27
What’s Floorplanning? 1 6 2 3 4 5 7 8 8 2 6 7 After floorplanning 4 5 1 3 9 / 27
B*-Tree 5 5 Yun-Chih Chang et al. (2000). “B*-Trees: A New Representation for Non-Slicing Floorplans”. In: Proc. DAC , pp. 458–463. 10 / 27
Classic Design Flow 7 ◮ Integer linear programming (ILP) based ◮ More complicated ILP formulation is develped in ICCAD’07 6 . 6 Wan-Ping Lee, Hung-Yi Liu, and Yao-Wen Chang (2007). “An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning”. In: Proc. ICCAD , pp. 650–655. 7 Wai-Kei Mak and Jr-Wei Chen (2007). “Voltage island generation under performance requirement for SoC designs”. In: Proc. ASPDAC , pp. 798–803. 11 / 27
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Overview Introduction Background: NP problem Background: Dynamic Programming DAC’07: Voltage Partitioning ICCAD’06: Voltage Assignment on Netlist ICCAD’07: Voltage Assignment on Slicing Floorplanning 13 / 27
NP-Completeness [Garey & Johnson,1979] 8 ◮ Decision Problem (Yes/No Problem) ◮ N P : Set of problems w. Nondeterministic Polynomial time algorithm ◮ P : Set of problems w. (Deterministic) Polynomial time algorithm ◮ N P -Complete : hardest problems in NP If a problem in NP -Complete solved in polynomial time → any problem in NP solved in polynomial time 8 Some contents & figures on this part come from Prof. Takahashi 13 / 27
NP-Completeness [Garey & Johnson,1979] 8 ◮ Decision Problem (Yes/No Problem) ◮ N P : Set of problems w. Nondeterministic Polynomial time algorithm ◮ P : Set of problems w. (Deterministic) Polynomial time algorithm ◮ N P -Complete : hardest problems in NP ◮ Conjecture: P � = NP If a problem in NP -Complete solved in polynomial time → any problem in NP solved in polynomial time 8 Some contents & figures on this part come from Prof. Takahashi 13 / 27
Polynomial Time Reduction ◮ Provides difficulty relation between problems ◮ SAT is NP -Complete → 3SAT, Hamilton, TSP, Coloring... 14 / 27
NP-Hardness [Garey & Johnson,1979] ◮ Optimization problem ◮ Is neither in NP nor in NP -Complete ◮ N P -hard if a related decision problem is NP -complete ◮ E.g. Travelling Salesman Problem (TSP) ◮ No polynomial time algorithm 15 / 27
Strategies of Algorithm Design 1. Check whether problem is easy or not? 2. If possible, prove is NP -hard or NP -complete 3. For easy problem (in P ): 4. For not easy problem (in NP -hard): 16 / 27
Overview Introduction Background: NP problem Background: Dynamic Programming DAC’07: Voltage Partitioning ICCAD’06: Voltage Assignment on Netlist ICCAD’07: Voltage Assignment on Slicing Floorplanning 17 / 27
Case 1: Calculating Binomial Coefficient 17 / 27
Case 1: Calculating Binomial Coefficient Question Can we have a better Algorithm? 17 / 27
Case 2: Knapsack Problem n � x i v i max i = 1 n � x i w i ≤ W s . t . i = 1 ◮ v i : value of object i ◮ w i : weight of object i ◮ x i ∈ { 0 , 1 } Question ◮ Design a Dynamic Programming Algorithm to Solve it. ◮ What is x i can be floating value? 18 / 27
Principle of Optimality In an optimal sequence of decisions or choices, each subsequence must also be optimal. 19 / 27
Overview Introduction Background: NP problem Background: Dynamic Programming DAC’07: Voltage Partitioning ICCAD’06: Voltage Assignment on Netlist ICCAD’07: Voltage Assignment on Slicing Floorplanning 20 / 27
9 9 Hung-Yi Liu, Wan-Ping Lee, and Yao-Wen Chang (2007). “A provably good approximation algorithm for power optimization using multiple supply voltages”. In: Proc. DAC , pp. 887–890. 20 / 27
◮ On perfect-number partition: https://en.wikipedia.org/wiki/Partition_problem ◮ Correction: 10 10 Tao Lin et al. (2010). “A revisit to voltage partitioning problem”. In: Proc. GLSVLSI , pp. 115–118. 21 / 27
Overview Introduction Background: NP problem Background: Dynamic Programming DAC’07: Voltage Partitioning ICCAD’06: Voltage Assignment on Netlist ICCAD’07: Voltage Assignment on Slicing Floorplanning 22 / 27
ICCAD’06: Voltage Assignment on Netlist 11 (a) Algorithm Flow (b) Notations Question: ◮ How to define a slack for each vertex v i ? ◮ Please provide a mathematical formulation minizing total power consumption. 11 Wan-Ping Lee, Hung-Yi Liu, and Yao-Wen Chang (2006). “Voltage island aware floorplanning for power and timing optimization”. In: Proc. ICCAD , pp. 389–394. 22 / 27
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◮ Further speed-up: dual to min-cost flow 12 ◮ Overcome reconverge issue: 13 12 Qiang Ma and Evangeline FY Young (2008). “Network flow-based power optimization under timing constraints in MSV-driven floorplanning”. In: Proc. ICCAD , pp. 1–8. 13 Yifang Liu and Jiang Hu (2009). “A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment”. In: Proc. ISPD , pp. 27–34. 23 / 27
14 Consistency Relaxation backward solution propagation (v 2 =1: v 4 =1)[ c=3, q=7] (v 2 =2: v 4 =2)[ c=2, q=5] v 2 (v 4 =1)[ c=3.1, q=8.2] (v 1 =1: v 2 =2, v 3 =2)[ c=5, q=3.5] v 1 v 4 (v 4 =2)[ c=2.9, q=8] (v 1 =2: v 2 =1, v 3 =2)[ c=5, q=4.4] (v 4 =3)[ c=2.7, q=7.9] v 3 (v 3 =1: v 4 =1)[ c=4, q=7] (v 3 =2: v 4 =2)[ c=3, q=6] 15 14 Yifang Liu and Jiang Hu (2009). “A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment”. In: Proc. ISPD , pp. 27–34. 24 / 27
14 Consistency Relaxation (v 2 =1: v 4 =1)[ c=3, q=7] (v 2 =2: v 4 =2)[ c=2, q=5] v 2 (v 4 =1)[ c=3.1, q=8.2] (v 1 =1: v 2 =2, v 3 =2)[ c=5, q=3.5] v 1 v 4 (v 4 =2)[ c=2.9, q=8] (v 1 =2: v 2 =1, v 3 =2)[ c=5, q=4.4] (v 4 =3)[ c=2.7, q=7.9] v 3 (v 3 =1: v 4 =1)[ c=4, q=7] (v 3 =2: v 4 =2)[ c=3, q=6] 16 14 Yifang Liu and Jiang Hu (2009). “A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment”. In: Proc. ISPD , pp. 27–34. 24 / 27
14 Consistency Relaxation (v 2 =1: v 4 =1)[ c=3, q=7] 1 or v 4 2 ? v 4 v 2 (v 4 =1)[ c=3.1, q=8.2] (v 1 =2: v 2 =1, v 3 =2)[ c=5, q=4.4] v 1 v 4 (v 4 =2)[ c=2.9, q=8] v 3 (v 3 =2: v 4 =2)[ c=3, q=6] 17 14 Yifang Liu and Jiang Hu (2009). “A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment”. In: Proc. ISPD , pp. 27–34. 24 / 27
14 Consistency Restoration forward solution propagation (v 2 =1) [a=3.6] v 2 (v 4 =1) [a= ,q=8.2] (v 4 =2) [a= ,q=8] (v 1 =2) [a=2] v 1 v 4 (v 4 =3) [a= ,q=7.9] v 3 D(v i ,v j ) V 4 =1 V 4 =2 V 4 =3 V 2 =1 1.2 3 2.2 (v 3 =2) [a=3.6] V 3 =2 3 2 2.2 18 14 Yifang Liu and Jiang Hu (2009). “A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment”. In: Proc. ISPD , pp. 27–34. 24 / 27
14 Consistency Restoration forward solution propagation (v 2 =1) [a=3.6] v 2 (v 4 =1) [a=6.6 ,q=8.2] (v 4 =2) [a=6.6 ,q=8] (v 1 =2) [a=2] v 1 v 4 (v 4 =3) [a=5.8 ,q=7.9] v 3 D(v i ,v j ) V 4 =1 V 4 =2 V 4 =3 V 2 =1 1.2 3 2.2 (v 3 =2) [a=3.6] V 3 =2 3 2 2.2 19 14 Yifang Liu and Jiang Hu (2009). “A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment”. In: Proc. ISPD , pp. 27–34. 24 / 27
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