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CDC TRG Special Meeting in NTU Thank you very very much for the - - PowerPoint PPT Presentation

Jul 07, 2023 286 likes •750 views

CDC TRG Special Meeting in NTU Thank you very very much for the support from NTU!!! Yoshihito Iwasaki (KEK) 2019/02/21 @ NTU Meeting Schedule Proposal Lets go all stages one by one CDC FE Merger TSF 2D

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SLIDE 1

CDC TRG Special Meeting in NTU

Yoshihito Iwasaki (KEK) 2019/02/21 @ NTU

Thank you very very much for the support from NTU!!!

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SLIDE 2

yoshihito.iwasaki@kek.jp

Meeting Schedule Proposal

  • Let’s go all stages one by one
  • CDC FE
  • Merger
  • TSF
  • 2D
  • Conventional 3D
  • 3D neuro
  • ETF
  • 3D Hough
  • GRL
  • Slow control (TRGCDC master)
  • B2L
  • GDL
  • Overall

2

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SLIDE 3

yoshihito.iwasaki@kek.jp

Belle-II TRG System

3

Korea U. National Taiwan U. National United U. KIT MPI TUM KEK Hanyang U. BINP

  • U. Pittsburgh
  • U. Hawaii

Virginia Tech

  • U. Hawaii

Indiana U. National Taiwan U. KEK

Global Reconstruction/Decision Logic (GRL and GDL)

L1 Trigger ～ 5μ sec after beam crossing

TOP

Multiplicity Topology Fine Timing Hit

ECL

4x4 Trigger Cell Energy Sum Cluster Count Timing High Threshold Low Threshold Bhabha Cluster

KLM

μ hit Forward Backward Barrel

CDC

TSF Opening Angle Back-to-back Track Count Timing 2D Tracker 3D Tracker 3D Muon Track Hadron Cluster

V New in Belle II

3D Neuro

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SLIDE 4

yoshihito.iwasaki@kek.jp

CDC Super Layer 8 CDC Super Layer 7 CDC Super Layer 6 CDC Super Layer 5 CDC Super Layer 4 CDC Super Layer 3 CDC Super Layer 2 CDC Super Layer 1 CDC Super Layer 0 160 x 6 wires = 20 x 48 160 x 6 wires = 20 x 48 192 x 6 wires = 24 x 48 224 x 6 wires = 28 x 48 256 x 6 wires = 32 x 48 288 x 6 wires = 36 x 48 320 x 6 wires = 40 x 48 352 x 6 wires = 44 x 48 384 x 6 wires = 48 x 48 UT3 Board In 40 GTX 8 GTH (as GTX) Track Segment Finder 8 UT3 Board In 40 GTX 4 GTH (as GTX) Track Segment Finder 7 UT3 Board In 40 GTX Track Segment Finder 6 UT3 Board In 36 GTX Track Segment Finder 5 UT3 Board In 32 GTX Track Segment Finder 4 UT3 Board In 28 GTX Track Segment Finder 3 UT3 Board In 24 GTX Track Segment Finder 2 UT3 Board In 20 GTX Track Segment Finder 1 UT3 Board 800 ch 800 ch 960 ch 1120 ch 1280 ch 1440 ch 1600 ch 1760 ch 1920 ch 81.280 Gbps 81.280 Gbps 97.536 Gbps 113.792 Gbps 130.048 Gbps 146.304 Gbps 162.56 Gbps 178.816 Gbps 195.072 Gbps In 20 GTX Track Segment Finder 0 20 links / 5 cables (81.28 Gbps max.) 20 links / 5 cables (81.28 Gbps max.) 24 links / 6 cables (97.536 Gbps max.) 28 links / 7 cables (113.792 Gbps max.) 32 links / 8 cables (130.048 Gbps max.) 36 links / 9 cables (146.304 Gbps max.) 40 links / 10 cables (162.56 Gbps max.) 44 links / 11 cables (178.816 Gbps max.) 48 links / 12 cables (195.072 Gbps max.) Out 11 GTH Out 19 GTH Out 11 GTH Out 19 GTH Out 11 GTH Out 20 GTH Out 12 GTH Out 20 GTH Out 12 GTH Merger (x12) Merger (x11) Merger (x10) Merger (x9) Merger (x8) Merger (x7) Merger (x6) Merger (x5) Merger (x5) 960 ch 162.56 Gbps 80 links / 20 cables (162.56 Gbps max.) CDC Front-End (x20) 960 ch 162.56 Gbps 80 links / 20 cables (162.56 Gbps max.) CDC Front-End (x20) 1152 ch 195.072 Gbps 96 links / 24 cables (195.072 Gbps max.) CDC Front-End (x24) 1344 ch 227.584 Gbps 112 links / 28 cables (227.584 Gbps max.) CDC Front-End (x28) 1536 ch 260.096 Gbps 128 links / 32 cables (260.096 Gbps max.) CDC Front-End (x32) 1728 ch 292.608 Gbps 144 links / 36 cables (292.608 Gbps max.) CDC Front-End (x36) 1920 ch 325.12 Gbps 160 links / 40 cables (325.12 Gbps max.) CDC Front-End (x40) 2112 ch 357.632 Gbps 176 links / 44 cables (357.632 Gbps max.) CDC Front-End (x44) 2304 ch 390.144 Gbps 192 links / 48 cables (390.144 Gbps max.) CDC Front-End (x48) UT3 Board 2D Tracker 0 UT3 Board 2D Tracker 1 Out 8 GTH In 10 GTH UT3 Board 2D Tracker 2 Out 8 GTH In 10 GTH 2D Tracker 3 UT3 Board Out 8 GTH In 10 GTH Out 8 GTH In 10 GTH 2 links x4 (20.3196 Gbps max. x4) 2 links x4 (20.3196 Gbps max. x4) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[12-14] OptH[16-18] OptH[20] OptH[21] OptH[12-14] OptH[16-18] OptH[20] OptH[21] OptH[12-14] OptH[16-18] OptH[20] OptH[21] OptH[12-14] OptH[16-18] OptH[20] OptH[21] 2 links x8 (20.3196 Gbps max. x8) [3 links / 1 cable] x 2 (30.4794 Gbps max. x 2) [3 links / 1 cable] x 2 (30.4794 Gbps max. x 2) [3 links / 1 cable] x 2 (30.4794 Gbps max. x 2) [3 links / 1 cable] x 2 (30.4794 Gbps max. x 2) [1 link / 1 cable] x8 (4.064 Gbps max x4) UT3 Board 3D Finder 0 Out 2 GTH In 1 GTH (as GTX) 11 GTH Unknown Board Neural Network 0 UT3 Board 3D Finder 2 Unknown Board Neural Network 2 UT3 Board 3D Finder 3 Unknown Board Neural Network 3 UT3 Board 3D Finder 1 Unknown Board Neural Network 1 OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] OptH[16] OptH[0-2] OptH[12] OptH[13] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-11] UT3 Board Event Timing & Low Pt 2 links x5 (20.3196 Gbps max. x5) 3 links x4 (30.4795 Gbps max. x4) In 22 GTH Out 8 GTX 2 GTH OptH[8-9] OptH[8-9] OptH[8-9] OptH[0-1] OptX[0] OptX[4] OptX[8] OptX[12] OptX[16] OptX[20] OptX[24] OptX[28] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[10-12] OptH[13-15] OptH[16-18] OptH[19-21] Belle2Link (HSLBs) OptH[10] OptH[18] OptH[10-11] OptH[12-13] OptH[14-15] OptH[16-17] OptH[10] 1 links x4 (10.1598 Gbps max. x4) 1 links x4 (10.1598 Gbps max. x4) 1 links x4 (10.1598 Gbps max. x4) 1 link (10.1598 Gbps max.) GRL Sub (Patch Panel) 2 links x5 (20.3196 Gbps max. x5) 2 links x5 (20.3196 Gbps max. x5) 2 links x5 (20.3196 Gbps max. x5) 2 links x5 (20.3196 Gbps max. x5) 2 links x8 (20.3196 Gbps max. x8) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[18] OptH[10-11] OptH[12-13] OptH[14-15] OptH[16-17] 2 links x4 (20.3196 Gbps max. x4) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] 2 links x8 (20.3196 Gbps max. x8) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-9] OptH[8-9] OptH[10] OptH[19] OptH[10-11] OptH[12-13] OptH[14-15] OptH[16-18] 2 links x4 (20.3196 Gbps max. x4) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] 2 links x8 (20.3196 Gbps max. x8) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-10] OptH[8-9] OptH[11] 2 links x4 (20.3196 Gbps max. x4) OptH[0-1] OptH[2-3] OptH[4-5] OptH[6-7] OptH[8-10] OptH[11] OptH[19] OptH[10-11] OptH[12-13] OptH[14-15] OptH[16-18] 8b10b GTP protocol User clock : 127 MHz Lane width : 16 bits Lane rate : 2.54 Gbps Actual data rate : 2.032 Gbps
  • Max. width : 64 bits/data clock * lane
8b10b GTX protocol User clock : 254 MHz Lane width : 16 bits Lane rate : 5.08 Gbps Actual data rate : 4.064 Gbps
  • Max. width : 128 bits/data clock * lane
raw-level GTH protocol User clock : 169.33 MHz Lane width : 64 bits Lane rate : 11.176 Gbps Actual data rate : 10.1598 Gbps (only 15/16 bits are used)
  • Max. width : 320 bits/data clock * lane
(2 modules in 1 board) OptH[22] OptH[23] 1 link x9 (10.1598 Gbps max. x9) 1 links (10.1598 Gbps max.) Out 2 GTH In 1 GTH (as GTX) 11 GTH Out 2 GTH In 1 GTH (as GTX) 11 GTH Out 2 GTH In 1 GTH (as GTX) 11 GTH Out 2 GTH In 1 GTH (as GTX) 11 GTH Out 2 GTH In 1 GTH (as GTX) 11 GTH Out 2 GTH In 1 GTH (as GTX) 11 GTH Out 2 GTH In 1 GTH (as GTX) 11 GTH

CDC Trigger

CDC Front-Ends (290) Mergers (73) Track Segment Finders (TSF, 9) Event Timing & Short Tracker (1) 2D Trackers (4) 3D Trackers (4 Conventional & 4 Neuro-3D) 4

  • 3 types of trackers
  • 2D tracker (Hough Finder)
  • Conventional 3D tracker
  • Neuro 3D tracker
  • Tracker output (track parameters) are sent to GRL
  • GRL is a master of CDC trigger
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SLIDE 5

yoshihito.iwasaki@kek.jp

CDC Front-end

  • Items
  • Maintain TRG output firmware
  • Manpower
  • YTL (KEK)
  • Problems
  • Noise hit reduction
  • Cross-talk reduction
  • Radiation damage of AVAGO modules
  • Do we need spares for AVAGO modules?
  • Should we monitor light yield of the front-end AVAGO module?
  • Monitoring tools
  • Hit rates
  • Noise hits?
  • Cross-talks?
  • CDC front-end upgrade
  • Only one wire layer (priority layer) of drift time are sent
  • If we send drift time of more layers, better tracking (fitting) would be

possible

  • Close contact with CDC FE development groups

5

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SLIDE 6

yoshihito.iwasaki@kek.jp

6 9

1 FE board read 3-layers X 16 cells 1-super layer is read by 2 FEs

Cyan : axial Pink : stereo white : cell-ID%16=0

  • range : cell-ID%8=0 && cell-ID%16!=0

Run 6364 beam background data

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SLIDE 7

yoshihito.iwasaki@kek.jp

7 10 X(horizontal) : TDC (nsec) 1 div = 10nsec Y(vertical) : Channel ID of FE number of hits channel per board > 15 Blue : ADCsum<20 Orange : ADCsum>=20 && ADCsum<500 Red : ADCsum >=500

35

4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5 10 15 20 25 30 35 40 45 50

35 36

4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5 10 15 20 25 30 35 40 45 50

36 37

4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5 10 15 20 25 30 35 40 45 50

37

  • Clusters are localized within the unit of readout board
  • Most of hit channels have almost same timing and small charge
  • > many hits come from cross talk

Remarks: larger TDC value is corresponding to faster timing

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SLIDE 8

yoshihito.iwasaki@kek.jp

8

Motivation

Motivation

CDC tracking efficiency significantly influenced by cross-talk. Introduction of a cut on the charge deposit (ADC) in the CDC. Illustration: event with 1 track detected by the SVD. No ADC cut: track not found. With ADC cut: track found.

  • S. Glazov, C. Praz

CDC meeting: ADC cut 32nd B2GM, 05.02.2019 2 / 12

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SLIDE 9

yoshihito.iwasaki@kek.jp

9

Motivation

ADC distribution of the CDC hits

Histograms below count hits with (without) an associated track. Low-ADC hits look like background.

Caveat: raw ADC, not corrected for its θ-dependence (see conclusion).

λ ≡ π

2 − θ: angle between a track and the plan ⊥ to the beam.

  • S. Glazov, C. Praz

CDC meeting: ADC cut 32nd B2GM, 05.02.2019 3 / 12

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SLIDE 10

yoshihito.iwasaki@kek.jp

10

Nanae Taniguchi (190207)

2

Motivation for the upgrade

  • Radiation damage

– AVAGO optical module for the trigger output – ~300Gy several years < 10 years?

  • Temperature problem
  • FADC

– The rate (30MHz) seems to be too slow as looking the X-ray signal for Fe-55 source. – Small pedestal spread – Time walk correction

  • ASD-ASIC ： basically OK

– Smaller under shoot – Shorter peaking time and lower noise level – Slightly longer shaping time TRG DAQ

reduction of power consumption is desired high sampling rate and higher resolution (bit) TRG opt. dead at ~300Gy DAQ opt. dead at ~500Gy

  • S. Uno at CDC-B2GM
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SLIDE 11

yoshihito.iwasaki@kek.jp

11

Nanae Taniguchi (190207)

3

Discussion with T. Uchida-san

  • T. Uchida will find new suitable FPGA.

– Less power consumption with similar (or better) performance

  • New ASIC will be developed.

– One expert (M. Miyahara: KEK system electronics group) has an interest to develop new ASIC. – Combined ASIC for ASD (+DAC) and FADC with lower power consumption

Outline M. Miyahara

  • LSI development for Belle II CDC readout
  • Purposes

– Lower power consumption – Higher rate and better resolution for FADC

  • Final target : (ASD + ADC)x8ch

– Present : ASD: 34mW/ch, ADC: 100mW/ch – Target : ASD :10mW/ch, ADC:10mW/ch

  • Process

– TSMC 65nm LP

  • S. Uno at CDC-B2GM
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SLIDE 12

yoshihito.iwasaki@kek.jp

12

Nanae Taniguchi (190207)

4

Status

  • Submission was done in the last Dec.
  • ASIC will be available at the end of March.
  • Fortunately, 0th –version is available.

Parameter Value # of Chs. 8 Analog gain

  • 1.1V/pC

Peaking time 8 ns Noise 4000 e @Cd=20 pF Power +5V, +3.3V Power consumption 34mW/ch Process BiCMOS 0.8 μm New ASIC Belle II

  • S. Uno at CDC-B2GM
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SLIDE 13

yoshihito.iwasaki@kek.jp

13

Nanae Taniguchi 17thB2GM

0 Gy Firmware download Power cycle 100 200 300 400 500 600 700 800 900 No TRG out replace optical module DAQ time out replace optical module No TRG out replace optical module No signal from 3-FADC chip DAC decrease by ~100mV No signal from 4-FADC chip

Results

try slow control every 10 min. Firmware download every 30 min. Power cycle every 30 min.

1.5V current increase up to 3A (2.6A at fjrst)

100 Gy/h 200 Gy/h 300 Gy/h

Belle2 10 years

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SLIDE 14

yoshihito.iwasaki@kek.jp

Mergers

  • Items
  • Maintain merger hardwares and firmware
  • Monitor (slow control)
  • Manpower
  • Hardware : JGS (NTU)
  • Firmware : YTL (KEK)
  • Do we need it?
  • Problems
  • Can’t download new mcs due to FPGA lock
  • Only a few spare boards
  • Monitoring (slow control)
  • We can monitor all wire hit rate but too much for the archiver
  • Front-end unit rate?
  • Future upgrades along with CDC FE
  • New board by Wang-san (NUU)
  • State machine frame for data transmission
  • Can NUU or NTU provide new merger modules?

14

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SLIDE 15

yoshihito.iwasaki@kek.jp

Track Segment Finder

  • Items
  • Maintain TSF firmwares
  • Performance study
  • Monitor (slow control)
  • Think about better logic / algorithm
  • Manpower
  • Firmware : Kai, SB (KIT)
  • Performance : JGS (NTU)
  • Slow control : YI (KEK)
  • New logic / algorithm : ?
  • Performance
  • We really need to know its performance
  • Problems
  • Monitor (slow control)
  • Future upgrade
  • GTH full speed data transmission?
  • Better logic?
  • Neighbor hit suppression
  • Robustness for cross-talk and noise hits
  • Better output timing adjustment to reduce effect of a long drift time
  • UT4?

15

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SLIDE 16

yoshihito.iwasaki@kek.jp

2D Track Finder

  • Itemss
  • Maintain 2D firmwares
  • Performance study
  • Monitor (slow control)
  • Think about better logic / algorithm
  • Manpower
  • Firmware : PC (NTU)
  • Performance : JGS (NTU)
  • KEK can maintain firmware : -> YTL (KEK)
  • Performance
  • Problems
  • Monitor (slow control)
  • Presently only through GRL
  • Future upgrade
  • UT4?
  • New algorithm?

16

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SLIDE 17

yoshihito.iwasaki@kek.jp

Conventional 3D Tracker

  • Itemss
  • Debug of existing firmware
  • Maintain firmware
  • Monitor (slow control)
  • Performance study
  • Manpower
  • Firmware : Jason (NTU)
  • Monitor (slow control)
  • Plans / milestones

17

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SLIDE 18

yoshihito.iwasaki@kek.jp

Neuro 3D

  • Itemss
  • Complete debugging
  • Maintain firmware
  • Monitor (slow control)
  • Performance study
  • Manpower
  • Firmware : SB (KIT)
  • Monitor and performance : SS ()
  • Monitor (slow control)
  • Plans / milestones
  • Future upgrade

18

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SLIDE 19

yoshihito.iwasaki@kek.jp

ETF

  • Items
  • Maintain firmware
  • Performance study
  • Monitor (slow control)
  • Think about better logic / algorithm
  • Manpower
  • Firmware, performance, monitor : HM (KU)
  • Need new manpower because HM will graduate in a year
  • Performance
  • Problems
  • Effects of noise and cross-talks
  • Monitor (slow control)
  • Future upgrade
  • If performance is not enough, new algorithm is necessary
  • 19
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SLIDE 20

yoshihito.iwasaki@kek.jp

3D Hough Finder

  • Items
  • Finalize algorithm
  • Implementation on FPGA
  • Implementation in our TRGCDC system
  • Manpower
  • SS
  • Plans and milestones
  • Do we need fitter to get better dz resolution?
  • 20
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SLIDE 21

yoshihito.iwasaki@kek.jp

GRL

  • Itemss
  • Maintain firmwares
  • Performance study
  • Monitor (slow control)
  • Manpower
  • YTL (KEK)
  • Performance
  • Problems
  • Latency with 3D tracks (not due to GRL itself)
  • Monitor (slow control)
  • New logic / algorithm
  • Short tracker (simple logic developed already)
  • Latency reduction in earlier stages
  • GTH full speed data transmission? (How about latency)
  • Track counting
  • Charge sum useful?
  • Back-to-back and opening angles

21

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SLIDE 22

yoshihito.iwasaki@kek.jp

Slow Control : TRGCDC Master

  • Items
  • Complete the first version
  • Maintenance
  • Manpower
  • TK (KEK)
  • Monitor (slow control)

22

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SLIDE 23

yoshihito.iwasaki@kek.jp

B2L

  • Items
  • Maintain firmware
  • Better implementation (to reduce resource usage on FPGA)
  • Manpower
  • HN, TK (recently join)
  • Problems
  • Better implementation
  • Can we reduce data size?
  • Can we reduce resource usage?

23

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SLIDE 24

yoshihito.iwasaki@kek.jp

GDL

  • Items
  • Firmware maintenance
  • Monitor (slow control)
  • Confirmation of logic correctness
  • Continues update to cope with new TRG bits
  • Manpower
  • HN (NTU) TK (KEK)
  • Problems
  • PSNM correctness
  • TMDL correctness
  • B2L readout
  • Clock speed
  • Data size
  • Timing errors
  • Plans
  • Move B2L readout logic to another UT3

24

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SLIDE 25

yoshihito.iwasaki@kek.jp

TRGCDC Overall

  • Items
  • Noise hits and cross-talks
  • How to cope with off-IP charged tracks with higher backgrounds
  • Do we need much powerful 3D? 3D hough?
  • 25
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SLIDE 26

yoshihito.iwasaki@kek.jp

Summary

26

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SLIDE 27

yoshihito.iwasaki@kek.jp

TRG : Requirements

  • ☑ High efficiency

almost 100% for Upsilon 4S events

  • No dead-time -> pipeline
  • Redundant and independent TRG logics -> 3 main TRG
  • ☒ Max. average rate 30 kHz @ 8x1035 cm–2s–1
  • Limited by DAQ
  • Good background reduction necessary
  • Flexible TRG logics to manage BG rates
  • Low level event reconstruction to identify BG
  • ☑ Latency

4.400 usec

  • Limit from SVD front-end
  • ☑ Timing precision

less than 10 nsec

  • Request from SVD front-end
  • ☑ Event separation

500 nsec

  • Request from DAQ was 200 nsec

27

☑ = ok, ☒ = unknown with peak luminosity

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SLIDE 28

yoshihito.iwasaki@kek.jp

General Status

  • TRG operation
  • System start-up : Jan. 15th
  • Cosmic trigger (+high rate Poisson) has been provided
  • GDL, GRL, and CDC-ETF are fine with high rate tests
  • After phase2
  • Some problematic hardwares were replaced (e.g. CDC TRG cables)
  • Firmwares have been updated to fix bugs or to improve performance
  • Preparation of monitoring tools is on going
  • Archiver : TRG rate monitoring
  • DQM : TRG rate and efficiencies
  • QAM : Performance stability check run by run
  • Preparation of TRG control softwares is on going
  • TRG type selection : physics / cosmic / random / etc
  • TRG configurations
  • TRG system start-up

28

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SLIDE 29

yoshihito.iwasaki@kek.jp

CDC TRG

  • 12 dead TRG cables were fixed
  • No dead region now
  • Latency reduction
  • By improving serial data transmission protocol
  • CDC merger : 200ns
  • CDC TSF : 130ns (expected)
  • CDC 2D : 130ns
  • CDC ETF : 130ns
  • TSF firmware
  • New state machine has been developed
  • For better maintenance (bug fix)
  • Better performance is expected
  • Test with cosmic is just started
  • Performance test is on going

29

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SLIDE 30

yoshihito.iwasaki@kek.jp

→ the eff. Decreased about 4% from the beginning to the end, not gradually. (‘’stepping down’’ around run 3800 and 5200) NOTE: this might mean the ‘decouple’ is not perfect. → ‘local’ drops at a few places: e.g. around run 3400 and run 5190. NOTE: these need studies to understand ~98%

local drop

CDC TRG : 2D Performance

  • 2D performance was measured
  • Effect of TSF performance is removed
  • It was quite high but unknown effects are seen
  • Further understanding is necessary

30

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SLIDE 31

yoshihito.iwasaki@kek.jp

CDC TRG : 3D

  • Conventional 3D
  • Logic debugging is just started
  • Core developer graduated so a new student is assigned
  • Almost impossible to be ready before phase3
  • Neuro 3D
  • Logic debugging by comparison of firmware output and simulation
  • utput is on going
  • Several bugs were fixed
  • Still some iterations of bug-fix and cosmic data taking are necessary
  • Hopefully it will be ready before phase3
  • Utilization of 3D info on GDL / GRL
  • We will use 3D info when we understand its performance (dz

resolution and efficiency)

31

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SLIDE 32

yoshihito.iwasaki@kek.jp

Global Reconstruction Logic : GRL

  • Jitter of each sub-triggers’ input and latency was

studied and adjusted

  • Only KLM is not tuned because of large KLM jitter
  • GRL matching logics (CDC, ECL, TOP, and KLM)

were confirmed by recent cosmic data

  • B2L suppress mode was developed to reduce read-
  • ut data size
  • CDC Short tracker was implemented by using

inner TSFs

  • For better track counting

32

  • Δ𝜚0,2

Δ𝜚0,4

  • Δ𝜚0,2 Δ𝜚0,4

– –

  • Δ𝜚0,2 Δ𝜚0,4

Algorithm (cont’d)

  • 3
  • 2
  • 1

1 2 3

  • 3
  • 2
  • 1

1 2 3

  • 3
  • 2
  • 1

1 2 3 1 unit = 5.625º SL0 SL2 SL4

slide-33
SLIDE 33

yoshihito.iwasaki@kek.jp

for CR shifter beam/physics...

  • n database to record trigger configulation

Global Decision Logic : GDL

  • New trigger bits are implemented
  • Delayed Bhabha for MC BG overlay
  • Abort gap bit requested by SVD group
  • Injection veto logic was updated
  • To cope with longer noise tail
  • Can work with HER and LER mix injections
  • Confirmation is necessary with real beam injection
  • Trigger type can be selected by CR shifter now

33

slide-34
SLIDE 34

yoshihito.iwasaki@kek.jp

TRG Slow Control (SLC)

  • SLC was missing in phase2 except for ECL TRG
  • SLC of GDL, GRL, CDC were made or under

implementation now

34

  • 1. TRG SLC structure
  • Feb. 4 2019, 32nd B2GM SLC Session

( 1 / 1 )

slide-35
SLIDE 35

yoshihito.iwasaki@kek.jp

TRG in Run Control Panel

35

  • 4. Run control panel
  • Feb. 4 2019, 32nd B2GM SLC Session

runcontrol(ecl/trg) processes on global(main) run control panel

( 4 / 4 )

slide-36
SLIDE 36

yoshihito.iwasaki@kek.jp

TRG Archiver, DQM

  • Archiver
  • ECL TRG
  • DQM of GDL and CDC were newly implemented

in release 03-00-01

  • # CDC tracks, GDL trigger rates, etc.
  • Will be checked when DQM is running on HLT

36

  • 2. TRG archived PV list
  • Feb. 4 2019, 32nd B2GM SLC Session

5 k are given for TRG group ( ~ 5 k are planned to be archived ) TRGECL archiving PV list : https://confluence.desy.de/pages/viewpage.action?pageId=94155341

PV # Comment Archived? Contact Person FAM temp. 104 52x2 Y C.H. Kim E.J. Jang TMM temp. 14 7x2 Y TC noise 576 ‐ N TC pedestal 576 ‐ Y TC hit‐rate 576 ‐ Y TC hit‐rate average ~100 FW, BR, BE, ALL, 𝜄 and ∅ Y TRG bits 44 ‐ Y Luminosity 2 Accelerator, Detector Y Total ~2000 ‐ ‐ ‐

※ PV lists: https://confluence.desy.de/display/BI/List+of+Archived+PVs

( 1 / 3 )

  • 2. TRG archived PV list
  • Feb. 4 2019, 32nd B2GM SLC Session

The PV lists of other sub‐triggers

PV # Comment Archived? Contact Person trggdl 672 inp/ftd/psn/dam_r/a_rate → (672) Y H.Nakazawa trggrl 6 rate_2D(3), rate_ECL(1), rate_KLM(1), rate_TOP(1) Y Y.T. Lai trgtsfn 2336 TSF hit rates (2336) N ‐ trgt3n 12 track rate from IP, track rate outside IP, valid cot (12=3x4) N ‐ trgetf 1 event timing rate (1) N ‐ Total ~3000 ‐ ‐ ‐ ( 2 / 3 )

※ PV lists: https://confluence.desy.de/display/BI/List+of+Archived+PVs

slide-37
SLIDE 37

yoshihito.iwasaki@kek.jp

Man Power

  • Lack of man power
  • CDC 2D : 1 NTU student, KEK will join
  • CDC 3D conventional : 1 NTU student just started
  • CDC ETF : 1 KU student, will leave soon
  • KLM : only Dmitri, he is busy with KLM DAQ
  • CDC TRG will have a special meeting in NTU

(2/21,22)

  • Man power will be one big issue there, but hopeless to have a new

institute joining CDC TRG

  • TRG expert shift
  • From March, we start TRG expert shifts
  • KEK : 3 staff
  • NTU : 1 staff + 2 students
  • Hanyang : 1 staff + 3 students
  • Pittsburgh : 2 staff + 1 student
  • KU : ?

37

slide-38
SLIDE 38

yoshihito.iwasaki@kek.jp

Injection Veto Studies : LER

  • Signals in an oscilloscope
  • yellow

: LER kicker signal

  • blue

: L1 signal

  • magenta: veto signal
  • green

: LER beam loss monitor

  • Veto parameters
  • vFull : full veto period, 100% dead time


100 revolutions

  • vGate : gate veto period, 20% dead time


600 revolutions

  • vLen : gate width


256 clocks (=2.048usec)

  • LER injection veto looks fine
  • Data analysis is necessary for fine tuning
  • f the veto parameters

38 Veto off Veto on

slide-39
SLIDE 39

yoshihito.iwasaki@kek.jp

Injection Veto Studies : HER

  • Signals in an oscilloscope
  • yellow

: HER kicker signal

  • blue

: L1 signal

  • magenta: veto signal
  • green

: HER beam loss monitor

  • Veto parameters
  • vFull : full veto period, 100% dead time


500 revolutions

  • vGate : gate veto period, 20% dead time


410 revolutions

  • vLen : gate width


256 clocks (=2.048usec)

  • HER injection veto looks failed
  • Injection noise tail was longer than

expected (~20msec)

  • GDL logic could veto up to 10 msec
  • Logic can be modified but veto period

fraction may be almost 100%

39 Veto off Veto on

slide-40
SLIDE 40

yoshihito.iwasaki@kek.jp

Expected TRG Rates

  • PS=1 for Bhabha in Phase2

40

Process C.S. (nb)

R@L=5.5x1033 (Hz) R@L=8x1035 (Hz)

TRG logic Upsilon(4S) 1.2 6.6 960

CDC 3trk(fff) ECL high energy(hie) ECL 4 clusters(c4)

Continuum 2.8 15.4 2200 μμ 0.8 4.4 640

CDC 2trk(ffo) etc

ττ 0.8 4.4 640 Bhabha 44 242 350 *

ECL Bhabha(bhabha, 3D bhabha)

γ-γ 2.4 13.2 19 * Two photon 13 71.5 10000

CDC 2trk(ffo) etc

Total 67 357.5 ~15000

Phase2 Lum. Record

slide-41
SLIDE 41

yoshihito.iwasaki@kek.jp

TRG Condition in Phase 2

  • Main triggers for physics (PS=1)
  • ffo (two-track) : 2D track > 1 & opening angle > 90° & !Bhabha
  • fff (three-track) : 2D track > 2
  • hie (high energy) : energy > 1 GeV & !Bhabha
  • c4 (four-cluster) : isolated cluster > 3 & !Bhabha
  • Triggers for calibrations (PS>1)
  • ff(PS=20), c2(PS=150), bhabha(PS=1), 3D bhabha(PS=1), many others
  • Triggers for MC background overlay
  • Delayed bhabha(PS=1), pseudo random(1Hz), revolution(1Hz)
  • Triggers for the dark sector
  • c1 & hie/lum, c3 & hie/lum, n1 & hie/lum, n3 & hie/lum
  • Timing decision
  • ECL timing only
  • Trigger condition (logic) were updated several times

when new triggers were available

  • 3D Bhabha, low-multi bits, dark sector bits, etc

41

slide-42
SLIDE 42

yoshihito.iwasaki@kek.jp

TRG Rate in Phase 2 : An Example

  • exp3, run4089 (6/19)
  • Av. lum.=10x1032, peak lum.=18x1032
  • Av. L1 rate=224Hz
  • fff 350Hz
  • higher than av. L1 rate because of multiple pulse counting in an event
  • ffo 120Hz
  • hie 65Hz
  • c4 25Hz
  • bhabha 34Hz
  • Only ~30% of total rate were from physics
  • Expected physics rate = 65Hz
  • ~70% are from calibration triggers and beam BG
  • Easy to tighten calibration triggers if necessary

42

slide-43
SLIDE 43

yoshihito.iwasaki@kek.jp

CDC Trigger Efficiency in Hadronic Events

43 run number 3600 3800 4000 4200 4400 4600 4800 cdc efficiency 0.2 0.4 0.6 0.8 1

cdc trigger efficiency vs run number

Christopher Hearty

~90%

slide-44
SLIDE 44

yoshihito.iwasaki@kek.jp

Mu-pair Yield in Offline : R. Garg

44

5

Ratio(Observed/Expected)

Firmware for 3 CDCTRG merger board (out of 73 boards) was broken.

(from Nakazawa-San)

  • Region C removed (bad ECL: 2008-2050).
  • Efficiency=28% (signal MC, no trigger efficiency included)

Single track efficiency ~ 85% Single track efficiency ~ 63% Why efficiency so low ? Why run dependent ?

slide-45
SLIDE 45

yoshihito.iwasaki@kek.jp

ECL Trigger Efficiency in Hadronic Events

45 run number 3600 3800 4000 4200 4400 4600 4800 ecl efficiency 0.2 0.4 0.6 0.8 1

ecl trigger efficiency vs run number

Christopher Hearty

~98% L1 TRG inefficiency for hadronic events = 10% (CDC) x 2% (ECL) = ~0.2%