[PPT] - Bringing NVIDIA GPUs to the PGAS/OpenSHMEM World: Challenges and PowerPoint Presentation

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Bringing NVIDIA GPUs to the PGAS/OpenSHMEM World: Challenges and Solutions

Dhabaleswar K. (DK) Panda The Ohio State University E-mail: panda@cse.ohio-state.edu http://www.cse.ohio-state.edu/~panda

GPU Technology Conference (GTC 2017) by

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High-End Computing (HEC): ExaFlop & ExaByte

10K-20K EBytes in 2016-2018

40K EBytes in 2020 ?

ExaFlop & HPC

ExaByte & BigData
Expected to have an ExaFlop system in 2021!

150-300 PFlops in 2017-18?

1 EFlops in 2021?

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Parallel Programming Models Overview

P1 P2 P3

Shared Memory

P1 P2 P3

Memory Memory Memory

P1 P2 P3

Memory Memory Memory Logical shared memory

Shared Memory Model SHMEM, DSM Distributed Memory Model MPI (Message Passing Interface) Partitioned Global Address Space (PGAS) Global Arrays, UPC, Chapel, X10, CAF, …

Programming models provide abstract machine models
Models can be mapped on different types of systems

– e.g. Distributed Shared Memory (DSM), MPI within a node, etc.

PGAS models and Hybrid MPI+PGAS models are gradually receiving

importance

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Overview of PGAS models (UPC and OpenSHMEM)
Limitations in PGAS models for GPU computing
Proposed Designs and Alternatives
Performance Evaluation
Conclusions

Outline

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Partitioned Global Address Space (PGAS) Models

Key features
Simple shared memory abstractions
Light weight one-sided communication
Easier to express irregular communication
Different approaches to PGAS
Languages
Unified Parallel C (UPC)
Co-Array Fortran (CAF)
X10
Chapel
Libraries
OpenSHMEM
UPC++
Global Arrays

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OpenSHMEM

SHMEM implementations – Cray SHMEM, SGI SHMEM, Quadrics SHMEM, HP SHMEM, GSHMEM
Subtle differences in API, across versions – example:

SGI SHMEM Quadrics SHMEM Cray SHMEM Initialization start_pes(0) shmem_init start_pes Process ID _my_pe my_pe shmem_my_pe

Made application codes non-portable
OpenSHMEM is an effort to address this:

“A new, open specification to consolidate the various extant SHMEM versions into a widely accepted standard.” – OpenSHMEM Specification v1.0 by University of Houston and Oak Ridge National Lab SGI SHMEM is the baseline

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Defines symmetric data objects that are globally

addressable

Allocated using a collective shmalloc routine
Same type, size and offset address at all

processes/processing elements (PEs)

Address of a remote object can be calculated based on info
f local object

OpenSHMEM Memory Model

Symmetric Object

b b

PE 0 PE 1

int main (int c, char *v[]) { int *b; start_pes(); b = (int *) shmalloc (sizeof(int)); shmem_int_get (b, b, 1 , 1); } (dst, src, count, pe) int main (int c, char *v[]) { int *b; start_pes(); b = (int *) shmalloc (sizeof(int));

}

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UPC: a parallel extension to the C standard
UPC Specifications and Standards:
Introduction to UPC and Language Specification, 1999
UPC Language Specifications, v1.0, Feb 2001
UPC Language Specifications, v1.1.1, Sep 2004
UPC Language Specifications, v1.2, 2005
UPC Language Specifications, v1.3, 2013
UPC Consortium
Academic Institutions: GWU, MTU, UCB, U. Florida, U. Houston, U. Maryland…
Government Institutions: ARSC, IDA, LBNL, SNL, US DOE…
Commercial Institutions: HP, Cray, Intrepid Technology, IBM, …
Supported by several UPC compilers
Vendor-based commercial UPC compilers: HP UPC, Cray UPC, SGI UPC
Open-source UPC compilers: Berkeley UPC, GCC UPC, Michigan Tech MuPC
Aims for: high performance, coding efficiency, irregular applications, …

Compiler-based: Unified Parallel C

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Global Shared Space: can be accessed by all the threads
Private Space: holds all the normal variables; can only be accessed by the local

thread

Examples:

shared int x; //shared variable; allocated with affinity to Thread 0 int main() { int y; //private variable }

UPC: Memory Model

Global Shared Space Private Space Thread 0 Thread 1 Thread 2 Thread 3

x y y y y

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Hierarchical architectures with multiple address spaces
(MPI + PGAS) Model

– MPI across address spaces – PGAS within an address space

MPI is good at moving data between address spaces
Within an address space, MPI can interoperate with other shared memory programming

models

Applications can have kernels with different communication patterns
Can benefit from different models
Re-writing complete applications can be a huge effort
Port critical kernels to the desired model instead

MPI+PGAS for Exascale Architectures and Applications

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Hybrid (MPI+PGAS) Programming

Application sub-kernels can be re-written in MPI/PGAS based on communication

characteristics

Benefits:

– Best of Distributed Computing Model – Best of Shared Memory Computing Model

Kernel1 MPI Kernel 2 MPI Kernel 3 MPI Kernel N MPI HPC Application Kernel 2 PGAS Kernel N PGAS

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Overview of the MVAPICH2 Project

High Performance open-source MPI Library for InfiniBand, Omni-Path, Ethernet/iWARP, and RDMA over Converged Ethernet (RoCE)

– MVAPICH (MPI-1), MVAPICH2 (MPI-2.2 and MPI-3.0), Started in 2001, First version available in 2002 – MVAPICH2-X (MPI + PGAS), Available since 2011 – Support for GPGPUs (MVAPICH2-GDR) and MIC (MVAPICH2-MIC), Available since 2014 – Support for Virtualization (MVAPICH2-Virt), Available since 2015 – Support for Energy-Awareness (MVAPICH2-EA), Available since 2015 – Support for InfiniBand Network Analysis and Monitoring (OSU INAM) since 2015

– Used by more than 2,750 organizations in 84 countries – More than 416,000 (> 0.4 million) downloads from the OSU site directly

– Empowering many TOP500 clusters (Nov ‘16 ranking)

1st, 10,649,600-core (Sunway TaihuLight) at National Supercomputing Center in Wuxi, China
13th, 241,108-core (Pleiades) at NASA
17th, 462,462-core (Stampede) at TACC
40th, 74,520-core (Tsubame 2.5) at Tokyo Institute of Technology

– Available with software stacks of many vendors and Linux Distros (RedHat and SuSE)

– http://mvapich.cse.ohio-state.edu

Empowering Top500 systems for over a decade

– System-X from Virginia Tech (3rd in Nov 2003, 2,200 processors, 12.25 TFlops) -> – Sunway TaihuLight (1st in Jun’16, 10M cores, 100 PFlops)

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MVAPICH2 Software Family

Requirements MVAPICH2 Library to use MPI with IB, iWARP and RoCE MVAPICH2 Advanced MPI, OSU INAM, PGAS and MPI+PGAS with IB and RoCE MVAPICH2-X MPI with IB & GPU MVAPICH2-GDR MPI with IB & MIC MVAPICH2-MIC HPC Cloud with MPI & IB MVAPICH2-Virt Energy-aware MPI with IB, iWARP and RoCE MVAPICH2-EA

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MVAPICH2-X for Advanced MPI and Hybrid MPI + PGAS Applications

MPI, OpenSHMEM, UPC, CAF, UPC++ or Hybrid (MPI + PGAS) Applications

Unified MVAPICH2-X Runtime InfiniBand, RoCE, iWARP

OpenSHMEM Calls MPI Calls UPC Calls

Unified communication runtime for MPI, UPC, OpenSHMEM, CAF available with MVAPICH2-X

1.9 (2012) onwards!

UPC++ support available since MVAPICH2-X 2.2RC1
Feature Highlights

– Supports MPI(+OpenMP), OpenSHMEM, UPC, CAF, UPC++, MPI(+OpenMP) + OpenSHMEM, MPI(+OpenMP) + UPC + CAF – MPI-3 compliant, OpenSHMEM v1.0 standard compliant, UPC v1.2 standard compliant (with initial support for UPC 1.3), CAF 2008 standard (OpenUH), UPC++ 1.0 – Scalable Inter-node and intra-node communication – point-to-point and collectives CAF Calls UPC++ Calls

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Application Level Performance with Graph500 and Sort

Graph500 Execution Time

J. Jose, S. Potluri, K. Tomko and D. K. Panda, Designing Scalable Graph500 Benchmark with Hybrid MPI+OpenSHMEM Programming Models,

International Supercomputing Conference (ISC’13), June 2013

J. Jose, K. Kandalla, M. Luo and D. K. Panda, Supporting Hybrid MPI and OpenSHMEM over InfiniBand: Design and Performance Evaluation,

Int'l Conference on Parallel Processing (ICPP '12), September 2012

5 10 15 20 25 30 35 4K 8K 16K Time (s)

No. of Processes

MPI-Simple MPI-CSC MPI-CSR Hybrid (MPI+OpenSHMEM) 13X 7.6X

Performance of Hybrid (MPI+ OpenSHMEM) Graph500 Design
8,192 processes
2.4X improvement over MPI-CSR
7.6X improvement over MPI-Simple
16,384 processes
1.5X improvement over MPI-CSR
13X improvement over MPI-Simple
J. Jose, K. Kandalla, S. Potluri, J. Zhang and D. K. Panda, Optimizing Collective Communication in OpenSHMEM, Int'l Conference on Partitioned

Global Address Space Programming Models (PGAS '13), October 2013.

Sort Execution Time 500 1000 1500 2000 2500 3000 500GB-512 1TB-1K 2TB-2K 4TB-4K Time (seconds) Input Data - No. of Processes MPI Hybrid 51%

Performance of Hybrid (MPI+OpenSHMEM) Sort

Application

4,096 processes, 4 TB Input Size
MPI – 2408 sec; 0.16 TB/min
Hybrid – 1172 sec; 0.36 TB/min
51% improvement over MPI-design

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Overview of PGAS models (UPC and OpenSHMEM)
Limitations in PGAS models for GPU computing
Proposed Designs and Alternatives
Performance Evaluation
Conclusions

Outline

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Limitations of OpenSHMEM for GPU Computing

OpenSHMEM memory model does not support disjoint memory address spaces -

case with GPU clusters

PE 0 Existing OpenSHMEM Model with CUDA

Copies severely limit the performance

PE 1 GPU-to-GPU Data Movement PE 0 cudaMemcpy (host_buf, dev_buf, . . . ) shmem_putmem (host_buf, host_buf, size, pe) shmem_barrier (…) host_buf = shmalloc (…) PE 1 shmem_barrier ( . . . ) cudaMemcpy (dev_buf, host_buf, size, . . . ) host_buf = shmalloc (…)

Synchronization negates the benefits of one-sided communication
Similar issues with UPC

cudaMemcpy (host_buf, dev_buf, . . . ) cudaMemcpy (host_buf, dev_buf, . . . ) shmem_barrier (…) shmem_barrier (…)

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Overview of PGAS models (UPC and OpenSHMEM)
Limitations in PGAS models for GPU computing
Proposed Designs and Alternatives
Performance Evaluation
Conclusions

Outline

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Global Address Space with Host and Device Memory

Host Memory Private Shared Host Memory Device Memory Device Memory Private Shared Private Shared Private Shared

shared space

n host memory

shared space

n device memory

N N N N

Extended APIs:
heap_on_device/heap_on_host
a way to indicate location of heap
host_buf = shmalloc (sizeof(int), 0);
dev_buf = shmalloc (sizeof(int), 1);

CUDA-Aware OpenSHMEM Same design for UPC PE 0 shmem_putmem (dev_buf, dev_buf, size, pe) PE 1 dev_buf = shmalloc (size, 1); dev_buf = shmalloc (size, 1);

S. Potluri, D. Bureddy, H. Wang, H. Subramoni and D. K. Panda, Extending

OpenSHMEM for GPU Computing, IPDPS’13

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After device memory becomes part of the global shared space:
Accessible through standard UPC/OpenSHMEM communication APIs
Data movement transparently handled by the runtime
Preserves one-sided semantics at the application level
Efficient designs to handle communication
Inter-node transfers use host-staged transfers with pipelining
Intra-node transfers use CUDA IPC
Possibility to take advantage of GPUDirect RDMA (GDR)
Goal: Enabling High performance one-sided communications semantics with GPU devices

CUDA-aware OpenSHMEM and UPC runtimes

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Inter-Node Communication

Pipelined data transfers through host memory - overlap between CUDA copies and IB transfers
Done transparently by the runtime
Designs with GPUDirect RDMA can help considerably improve performance
Hybrid design:

– GPUDirect RDMA – Pipeline 1 Hop – Proxy-based design

HOST

IOH

HOST

IOH

GPU1 GPU0

Inter-Node P0 P1

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Overview of PGAS models (UPC and OpenSHMEM)
Limitations in PGAS models for GPU computing
Proposed Designs and Alternatives
Performance Evaluation
Conclusions

Outline

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Using IPC for intra-node communication
Small messages – 3.4X improvement for 4Byte messages
Large messages – 5X for 4MByte messages

Shmem_putmem Intra-node Communication (IPC)

Small Messages Large Messages

5 10 15 20 25 30 1 4 16 64 256 1K 4K Latency (usec) Message Size (Bytes) 500 1000 1500 2000 2500 3000 16K 64K 256K 1M 4M Latency (usec) Message Size (Bytes)

5X 3.4X Based on MVAPICH2X-2.0b + Extensions Intel WestmereEP node with 8 cores 2 NVIDIA Tesla K20c GPUs, Mellanox QDR HCA CUDA 6.0RC1

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2 4 6 8 10 1 4 16 64 256 1K 4K IPC GDR

Small Message shmem_put D-H

Message Size (bytes)

Latency (us)

GDR for small and medium message sizes
IPC for large message to avoid PCIe bottlenecks
Hybrid design brings best of both
2.42 us Put D-H latency for 4 Bytes (2.6X improvement) and 3.92 us latency for 4 KBytes
3.6X improvement for Get operation
Similar results with other configurations (D-D, H-D and D-H)

2 4 6 8 10 12 14 1 4 16 64 256 1K 4K IPC GDR

Small Message shmem_get D-H

Message Size (bytes)

Latency (us) 2.6X 3.6X

Shmem_putmem Intra-node Communication (GDR Enhancement)

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Small messages benefit from selective CUDA registration – 22% for 4Byte messages
Large messages benefit from pipelined overlap – 28% for 4MByte messages
S. Potluri, D. Bureddy, H. Wang, H. Subramoni and D. K. Panda, Extending OpenSHMEM for GPU Computing, Int'l Parallel

and Distributed Processing Symposium (IPDPS '13)

Shmem_putmem Inter-node Communication (Pipeline)

Small Messages Large Messages

5 10 15 20 25 30 35 1 4 16 64 256 1K 4K Latency (usec) Message Size (Bytes) 500 1000 1500 2000 2500 3000 16K 64K 256K 1M 4M Latency (usec) Message Size (Bytes)

28% 22%

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GDR for small/medium message sizes
Host-staging for large message to avoid PCIe

bottlenecks

Hybrid design brings best of both
3.13 us Put latency for 4B (6.6X improvement ) and 4.7

us latency for 4KB

9X improvement for Get latency of 4B

5 10 15 20 25 1 4 16 64 256 1K 4K Host-Pipeline GDR

Small Message shmem_put D-D

Message Size (bytes)

Latency (us)

200 400 600 800 8K 32K 128K 512K 2M Host-Pipeline GDR

Large Message shmem_put D-D

Message Size (bytes)

Latency (us)

5 10 15 20 25 30 35 1 4 16 64 256 1K 4K Host-Pipeline GDR

Small Message shmem_get D-D

Message Size (bytes)

Latency (us) 6.6X 9X

Shmem_putmem Inter-node Communication (GDR and Proxy Enhancement)

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Execution time (sec) Number of GPU Nodes Host-Pipeline Enhanced-GDR

Platform: Wilkes (Intel Ivy Bridge + NVIDIA Tesla K20c + Mellanox Connect-IB)
New designs achieve 20% and 19% improvements on 32 and 64 GPU nodes for 2Kx2K input size

Application Evaluation: 2DStencil

19% 2DStencil 2Kx2K

45 %

2DStencil 1Kx1K

K . Hamidouche, A. Venkatesh, A. Awan, H. Subramoni, C. Ching and D. K. Panda, Exploiting GPUDirect RDMA in Designing High Performance OpenSHMEM for GPU Clusters. IEEE Cluster 2015

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Platform: Wilkes (Intel Ivy Bridge + NVIDIA Tesla K20c +

Mellanox Connect-IB)

Platform: CSCS (CS-Storm based): Haswell + NVIDA K80+ IB

FDR

K. Hamidouche, A. Venkatesh, A. Awan, H. Subramoni, C. Ching and D.
K. Panda, Exploiting GPUDirect RDMA in Designing High Performance

OpenSHMEM for GPU Clusters. Elsevier PARCO Journal, Oct 2016

Application Evaluation: GPULBM

Wilkes CSCS

Redesign the application
CUDA-Aware MPI : Send/Recv=> hybrid CUDA-Aware

MPI+OpenSHMEM

cudaMalloc =>shmalloc(size,1);
MPI_Send/recv => shmem_put + fence
45% benefits

45 %

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Overview of PGAS models (UPC and OpenSHMEM)
Limitations in PGAS models for GPU computing
Proposed Designs and Alternatives
Performance Evaluation
Conclusions

Outline

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PGAS models offer lightweight synchronization and one-sided

communication semantics

Low-overhead synchronization is suited for GPU architectures
Extensions to the PGAS memory model needed to efficiently support

CUDA-Aware PGAS models

High-performance GDR-based design for OpenSHMEM is proposed
Plan on exploiting the GDR-based designs for UPC and UPC++
Enhanced designs are planned to be incorporated into MVAPICH2-X

Conclusions

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Third International Workshop on Communication Architectures for HPC, Big Data, Deep Learning and Clouds at Extreme Scale ExaComm 2017

ExaComm 2017 will be held with the International Supercomputing Conference (ISC ‘17), at Frankfurt, Germany on Thursday, June 22nd, 2017 http://nowlab.cse.ohio-state.edu/exacomm/

Keynote Speaker: Dr. Jeffrey S. Vetter, Group Leader, Future Technologies Group at Oak Ridge National Laboratory

A set of talks from leaders in academia, industry and national laboratories, refereed research papers and a panel

ExaComm 2016 was held with the International Supercomputing Conference (ISC ‘16), at Frankfurt, Germany, June 23rd, 2016 http://nowlab.cse.ohio-state.edu/exacomm_16/ ExaComm 2015 was held with the International Supercomputing Conference (ISC ‘15), at Frankfurt, Germany, July 16th, 2015 http://nowlab.cse.ohio-state.edu/exacomm_15/

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August 14-16, 2017; Columbus, Ohio, USA
The MUG meeting provides an open forum for all attendees (users, system administrators,

researchers, engineers, and students) to discuss and share their knowledge on using MVAPICH2, MVAPICH2-X, MVAPICH2-GDR, MVAPICH2-MIC, MVAPICH2-Virt, MVAPICH2-EA, and OSU INAM

n large-scale systems and for a diverse set of applications.
The event will include

– A set of talks from experts in the field – Presentations from the MVAPICH2 team on tuning and optimization strategies for various components – Trouble shooting guidelines – Contributed presentations – An open mic session, and – An interactive/hands-on session with the MVAPICH2 developers in a one-to-one manner to discuss issues and problems.

More details at http://mug.mvapich.cse.ohio-state.edu/

Upcoming 5th Annual MVAPICH User Group (MUG) Meeting

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Funding Acknowledgments

Funding Support by Equipment Support by

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Personnel Acknowledgments

Current Students

–

A. Awan (Ph.D.)

–

R. Biswas (M.S.)

–

M. Bayatpour (Ph.D.)

–

S. Chakraborthy (Ph.D.)

Past Students

–

A. Augustine (M.S.)

–

P. Balaji (Ph.D.)

–

S. Bhagvat (M.S.)

–

A. Bhat (M.S.)

–

D. Buntinas (Ph.D.)

–

L. Chai (Ph.D.)

–

B. Chandrasekharan (M.S.)

–

N. Dandapanthula (M.S.)

–

V. Dhanraj (M.S.)

–

T. Gangadharappa (M.S.)

–

K. Gopalakrishnan (M.S.)

–

R. Rajachandrasekar (Ph.D.)

–

G. Santhanaraman (Ph.D.)

–

A. Singh (Ph.D.)

–

J. Sridhar (M.S.)

–

S. Sur (Ph.D.)

–

H. Subramoni (Ph.D.)

–

K. Vaidyanathan (Ph.D.)

–

A. Venkatesh (Ph.D.)

–

A. Vishnu (Ph.D.)

–

J. Wu (Ph.D.)

–

W. Yu (Ph.D.)

Past Research Scientist

–

K. Hamidouche

–

S. Sur

Past Post-Docs

–

D. Banerjee

–

X. Besseron

– H.-W. Jin –

W. Huang (Ph.D.)

–

N. Islam (Ph.D.)

–

W. Jiang (M.S.)

–

J. Jose (Ph.D.)

–

S. Kini (M.S.)

–

M. Koop (Ph.D.)

–

K. Kulkarni (M.S.)

–

R. Kumar (M.S.)

–

S. Krishnamoorthy (M.S.)

–

K. Kandalla (Ph.D.)

–

P. Lai (M.S.)

–

J. Liu (Ph.D.)

–

M. Luo (Ph.D.)

–

A. Mamidala (Ph.D.)

–

G. Marsh (M.S.)

–

V. Meshram (M.S.)

–

A. Moody (M.S.)

–

S. Naravula (Ph.D.)

–

R. Noronha (Ph.D.)

–

X. Ouyang (Ph.D.)

–

S. Pai (M.S.)

–

S. Potluri (Ph.D.)

– M.-W. Rahman (Ph.D.)

– C.-H. Chu (Ph.D.) –

S. Guganani (Ph.D.)

–

J. Hashmi (Ph.D.)

–

H. Javed (Ph.D.)

–

J. Lin

–

M. Luo

–

E. Mancini

Current Research Scientists

–

X. Lu

–

H. Subramoni

Past Programmers

–

D. Bureddy

–

M. Arnold

–

J. Perkins

Current Research Specialist

–

J. Smith

–

M. Li (Ph.D.)

–

D. Shankar (Ph.D.)

–

H. Shi (Ph.D.)

–

J. Zhang (Ph.D.)

–

S. Marcarelli

–

J. Vienne

–

H. Wang

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