BabelFish: Fusing Address Translations for Containers
Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, and Josep Torrellas University of Illinois at Urbana-Champaign skarlat2@illinois.edu ISCA 2020
BabelFish: Fusing Address Translations for Containers Dimitrios - - PowerPoint PPT Presentation
BabelFish: Fusing Address Translations for Containers Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, and Josep Torrellas University of Illinois at Urbana-Champaign skarlat2@illinois.edu ISCA 2020 Conventional Cloud
Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, and Josep Torrellas University of Illinois at Urbana-Champaign skarlat2@illinois.edu ISCA 2020
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Hardware
Hypervisor
Lib App
Guest OS
Lib App
Guest OS
Virtual Machines
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Lib App
Container Engine
Lib App Lib App Hardware
Operating System
Containers
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Shared Data Pages
Library
Container Engine
Hardware
Operating System
Application Binary
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Shared Data Pages
Library
Container Engine
Hardware
Operating System
Application Binary
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Shared Data Pages
Library
Container Engine
Hardware
Operating System
Application Binary
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“The Babel fish is small, yellow, leech-like, and probably the oddest thing in the Universe. The practical upshot of all this is that if you stick a Babel fish in your ear you can instantly understand anything said to you in any form of language.” The Hitchhiker's Guide to the Galaxy – Douglas Adams
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Main Memory Core L3 Cache L1 Cache L2 Cache TLB
Page Tables A
PA 4 VA 1
PA 4
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
à “Page Walk” = Fetch entry from page table TLB Miss Issue LD VA 1
PA4 VA1
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PCID
Existing Process Context IDentifiers (PCID)
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Main Memory
PA 4
Page Tables B Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PCID
PA4 VA1
Issue LD VA 1 à “Page Walk” = Fetch entry from page table TLB Miss
PCID PA4 VA1
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Main Memory
PA 4
Page Tables B Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PA4 VA1
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Main Memory
PA 4
Page Tables B Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PA4 VA1
CCID
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Main Memory
PA 4
Page Tables B Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PA4 VA1
CCID PC
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Main Memory
PA 4
Page Tables B Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PA4 VA1
PA6 VA1 CCID PC
CCID PC
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PCID
PA 4 VA 1 PA 4 VA 1
PA4 VA1
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
PA4 VA1 PCID PA4 VA1 PCID
Page Tables B
PA 4 VA 1 PA 4 VA 1 PA 4 VA 1 PA 4 VA 1 PA 4 VA 1
PA4 VA1
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
Page Tables B
PA 4 VA 1 P
P
Present bit
PA 4
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Main Memory Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
Page Tables B
PA 4 VA 1 P
P
Present bit currently cleared
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Main Memory Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
Page Tables B
PA 4 VA 1 P
P
Issue LD VA 1
PA4 VA1
P
Page Fault!
Storage PA 4
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
Page Tables B
PA 4 VA 1 P
P
Issue LD VA 1 Page Fault!
Storage Present bit set Present bit remains cleared
P
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Main Memory
PA 4
Page Tables A Core L3 Cache L1 Cache L2 Cache TLB
PA 4 VA 1
Page Tables B
PA 4 VA 1 P P
Page Fault!
Issue LD VA 1
PA4 VA1
P
Present bit set
P P
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pmd_t pte_t PGD PUD PMD PTE CR30
47 … 39 38 … 30 29 … 21 20 … 12 11 … 0 9-bits 9-bits 9-bits 9-bits 12-bits
+ + + Virtual Address To TLB +
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pmd_t pte_t PGD PUD PMD CR30
47 … 39 38 … 30 29 … 21 20 … 12 11 … 0 9-bits 9-bits 9-bits 9-bits 12-bits
+ + + Virtual Address To TLB + PTE pmd_t PGD PUD PMD CR31 + + + pte_t PTE + To TLB
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pmd_t pte_t PGD PUD PMD CR30
47 … 39 38 … 30 29 … 21 20 … 12 11 … 0 9-bits 9-bits 9-bits 9-bits 12-bits
+ + + Virtual Address To TLB + PTE pmd_t PGD PUD PMD CR31 + + + pte_t PTE + To TLB
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pmd_t pte_t PGD PUD PMD PTE CR30
47 … 39 38 … 30 29 … 21 20 … 12 11 … 0 9-bits 9-bits 9-bits 9-bits 12-bits
+ + + + Virtual Address To TLB pmd_t PGD PUD PMD CR31 + + +
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Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
L2 Cache Miss, L3 Cache Miss, Main Memory Hit
Page Walk Cache (PWC)
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Issue LD V1 Core 0 L1 TLB Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault L2 TLB Miss PWC Miss
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Issue LD V1 Core 0 L1 TLB Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault L2 TLB Miss PWC Miss
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Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
33
Issue LD V1 Core 0 L1 TLB Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk
PUD Walk PMD Walk PTE Walk
L2 Cache Miss, L3 Cache Hit
L2 TLB Miss PWC Miss
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Issue LD V1 Core 0 L1 TLB Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk
PUD Walk PMD Walk PTE Walk
L2 Cache Miss, L3 Cache Hit
Issue LD V1 Core 0 L1 TLB Hit L2 TLB Miss PWC Miss
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Issue LD V1 Core 0 L1 TLB Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Time
Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault
Issue LD V1 Core 0 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk PUD Walk PMD Walk PTE Walk Page Fault Issue LD V1 Core 1 L1 TLB Miss L2 TLB Miss PWC Miss PGD Walk
PUD Walk PMD Walk PTE Walk
L2 Cache Miss, L3 Cache Hit
Issue LD V1 Core 0 L1 TLB Hit
L2 TLB Miss PWC Miss
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2 containers per core 3 containers per core
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5-minute run on a real machine
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5-minute run on a real machine
39
5-minute run on a real machine
40
Active
5-minute run on a real machine
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After Merging Active
5-minute run on a real machine
42
5-minute run on a real machine
After Merging Active
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55%
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Dimitrios Skarlatos, Umur Darbaz, Bhargava Gopireddy, Nam Sung Kim, and Josep Torrellas University of Illinois at Urbana-Champaign skarlat2@illinois.edu ISCA 2020