Automatic Data Path Extraction in Large-Scale Register-Transfer Level Designs Wei Song, Jim Garside and Doug Edwards School of Computer Science, the University of Manchester Manchester M13 9PL United Kingdom 02/06/2014 Advanced Processor Technologies Group The School of Computer Science
Motivation • Data path extraction is important – Hardware verification – Synthesis for asynchronous circuits – System partition • Methodology – State-space analysis • actuate but slow and not scalable – Pattern matching • Fast, scalable but inaccurate • Accuracy depends on accurate type recognition Advanced Processor Technologies Group School of 02/06/2014 2 Computer Science
Tool Flow Bison+Flex, support A new graphic abstraction synthesizable Verilog to reveal relations between 2001. Verilog signals. Verilog RTL Abstract Signal-level Verilog RTL Parser Syntax Tree DFG Verilog RTL Data Path Extraction Data Path Only Graphic Remove Signal-level DFG Trimming Control Arcs Remove control Still directly mapped with Remove control related signals. relations. the AST. Possible for code extraction. Advanced Processor Technologies Group School of 02/06/2014 3 Computer Science
Signal-Level Data Flow Graph (DFG) module GCD (Clock,Reset,Load,A,B,Done,Y); A Greatest Common Divider (GCD) Calculator input Clock,Reset,Load; input [7:0] A,B; output Done; output [7:0] Y; A_P Reset_P Load_P B_P Clock_P reg A_lessthan_B, Done; reg [7:0] A_New, A_Hold, B_Hold, Y; I I I I I always @(posedge Clock) Reset A Clock if(Reset) begin Load B A_Hold = 0; B_Hold = 0; end else if(Load) begin A_Hold = A; B_Hold = B; end else if(A_lessthan_B) begin A_Hold = B_Hold; A_lessthan_B B_Hold = A_New; end else A_Hold = A_New; B_Hold FF FF A_Hold always @(A_Hold or B_Hold) A_New if(A_Hold >= B_Hold) begin A_lessthan_B = 0; I i_port A_New = A_Hold - B_Hold; end else begin O o_port A_lessthan_B = 1; A_New = A_Hold; wire end FF register always @(A_Hold or B_Hold) Done Y if(B_Hold == 0) begin Done = 1; Y = A_Hold; MODULE module end else begin clock Done = 0; Y = 0; end Y_P Done_P control endmodule O O data Advanced Processor Technologies Group School of 02/06/2014 4 Computer Science
Definition of a Signal-Level DFG A_P Reset_P Load_P B_P Clock_P I I I I I Reset A Clock Load B A signal-level DFG is a directed multi-graph denoted by a six-tuple: DFG ( , , V AT F T F , , , ) V V A A A_lessthan_B V a finite set of nodes representing Verilog components (signal and m odule) B_Hold FF FF A_Hold A V V a finite set of arcs connecting nodes A_New T a set of node types { reg wire in out module , , , , } I i_port V F : V T map types to nodes O o_port V V T a set of arc types { control d , ata clock reset , , } wire A F : A T map types to arcs FF register Done A A Y MODULE module clock Y_P Done_P control O O data Advanced Processor Technologies Group School of 02/06/2014 5 Computer Science
Node insertion input Clock,Reset,Load; input [7:0] A,B; A_P Reset_P Load_P B_P Clock_P output Done; I I I I I output [7:0] Y; reg A_lessthan_B, Done; Reset A Load B Clock reg [7:0] A_New, A_Hold, B_Hold, Y; always @(posedge Clock) if(Reset) begin A_lessthan_B A_Hold = 0; B_Hold = 0; B_Hold end else if(Load) begin FF FF A_Hold A_Hold = A; B_Hold = B; A_New end else if(A_lessthan_B) begin A_Hold = B_Hold; B_Hold = A_New; end else A_Hold = A_New; Done Y always @(A_Hold or B_Hold) if(B_Hold == 0) begin Latch will be detected Done = 1; Y = A_Hold; by case analysis. Y_P Done_P end else begin O O Done = 0; Y = 0; end Advanced Processor Technologies Group School of 02/06/2014 6 Computer Science
Type Estimation of Arcs Relation Tree always @(posedge Clock) if(Reset) begin A_New A_Hold = 0; B_Hold = 0; B_Hold end else if(Load) begin A_Hold = A_New A_Hold = A; B_Hold = B; A A_lessthan_B end else if(A_lessthan_B) begin A_Hold = B_Hold; If(A_lessthan_B) Load B_Hold = A_New; 0 end else A_Hold = A_New; Reset Clock A_Hold = 0 If(Reset) (posedge Clock) Reset A Clock Load A_Hold control recognition: A_lessthan_B if(sig) Arc connection case(sig) FF A_Hold in DFG C = sig?A:B A_New D = mem[addr] Advanced Processor Technologies Group School of 02/06/2014 7 Computer Science
Remove Control Arcs A_P A_P Reset_P Load_P Reset_P Load_P B_P Clock_P B_P Clock_P I I I I I I I I I I Reset A Clock Reset A Clock Load B Load B A_lessthan_B A_lessthan_B B_Hold B_Hold FF FF FF FF A_Hold A_Hold A_New A_New Done Done Y Y Y_P Done_P Y_P Done_P O O O O Advanced Processor Technologies Group School of 02/06/2014 8 Computer Science
Recursively Remove Dangling Components A_P Reset_P Load_P B_P Clock_P A_P B_P I I I I I I I Nodes to be Reset A Clock Load B A B recursively removed A_lessthan_B dangling B_Hold FF FF B_Hold A_Hold FF FF A_Hold wire A_New A_New dangling FF FF dangling O Done Y output Y dangling I input Y_P Done_P Y_P O O O dangling module module Advanced Processor Technologies Group School of 02/06/2014 9 Computer Science
Hierarchical Designs (SHA-3 Encoder) in out automatic generated data path DFG FF in the manual in_P out_P I O round one counter const round out in FF extracted data path round_in round round_out rconst i rc FF MODULE MODULE Advanced Processor Technologies Group School of 02/06/2014 10 Computer Science
Large-Scale Test Cases Signal al-le leve vel l DFG Data path DFG Time e Designs gns (s) (s) I/O Module Signal I/O Module Signal OR1200 52 37 2074 40 33 1142 1 RSD 7 24 1063 3 23 659 <1 NOVA 19 140 7043 9 103 4279 10 OR1200: A 5-stage OpenRISC processor. RSD: An industrial standard Reed-Solomon decoder. NOVA: An FPGA proven H.264/AVC baseline decoder. Intel Core TM 2 Due 3.00 GHz with 2GB memory Advanced Processor Technologies Group School of 02/06/2014 11 Computer Science
Possible Usages Signal-level DFG • – Code extraction – Controller detection* – Interface recognition (Memory, bus, handshake) Data path extraction • – Data-flow analysis by switching back-annotation – System partition * Wei Song and Jim Garside. Automatic controller detection for large scale RTL designs. In Proc. of EUROMICRO Conference on Digital System Design (DSD), Santander, Spain, pp. 884 – 851, September 2013 Advanced Processor Technologies Group School of 02/06/2014 12 Computer Science
Conclusion Signal-level DFG • – A graphic representation of signal relations in RTL. – A typed and hierarchical multi-graph. Data path extraction • – Trim all control related arcs and nodes. – Automatic control/data recognition. – Able to process large-scale designs. Advanced Processor Technologies Group School of 02/06/2014 13 Computer Science
Implementation and Test Environment Verilog parser • Bison, Flex and Vpreprocessor (Verilog Perl tool) [1] – C++ STL based abstract syntax tree – Signal-level DFG • Boost Graphic Library (data structure) – Open Graph Drawing Framework (automatic layout) [2] – PugiXML (file format) – Qt (diagram drawer) – User interface • Asynchronous Verilog Synthesiser [3] – Command line UI: embedded Tcl with self-defined commands – [1] http://www.veripool.org/verilog-perl [2] http://www.ogdf.net [3] https://github.com/wsong83/Asynchronous-Verilog-Synthesiser Advanced Processor Technologies Group School of 02/06/2014 14 Computer Science
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