ASYMMETRICAL DOUBLE GATE (ADG) MOSFETs COMPACT MODELING M. Reyboz, - - PowerPoint PPT Presentation

ASYMMETRICAL DOUBLE GATE (ADG) MOSFETs COMPACT MODELING

• M. Reyboz, O. Rozeau, T. Poiroux, P. Martin

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2005 OUTLINE

I INTRODUCTION II ADG ARCHITECTURE III MODELING DIFFICULTIES IV DIFFERENT WAYS OF MODELING V IMPLICIT ANALYTICAL MODEL: ITERATIVE RESOLUTION VI EXPLICIT ANALYTICAL MODEL: FULLY ANALYTICAL EXPRESSIONS VII CONCLUSION

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2005 INTRODUCTION

GENERAL CONTEXT

WHY ARE WE INTERESTED IN MODELING ADG MOSFETs?

• New Devices

– classical CMOS technologies + forecasts of the ROADMAP = ?? – New devices: GAA, FinFET, SON & planar DG

• ADG MOSFET

– Excellent channel control – Design flexibility with a second gate independently driven

• Model: to take advantage of this new device designers

need a model

• Compact Model: to design new circuits

90 nm 22 nm 45 nm

Bulk CMOS PD SOI CMOS FD SOI CMOS New devices

2004 2010 2016 2007

65 nm

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2005 ADG ARCHITECTURE

DIFFERENCES BETWEEN SYMMETRICAL (SDG) AND ASYMMETRICAL (ADG) DG MOSFETs

Front gate Back gate

PICTURE: ADG MOSFET M.Vinet et al, SSDM 2004

Drain Source

Channel SCHEMATIC: DG MOSFET

Tox1 Tox2

O

x Source Drain Front gate Back gate y Tsi Silicon film

L

Vg1 Vg2

Front oxide Back oxide

The asymmetry of the structure: ! gate oxide thicknesses ! gate voltages ! or/and gate work functions

22nm node

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2005 MODELING DIFFICULTIES

BASIC EQUATIONS OF ADG

POISSON EQUATION & ITS FIRTS INTEGRATION

si

n q dx d ε ψ .

2 2

=

                − −         − = −

t imref s t imref s si i t s s

u u n u q E E φ ψ φ ψ ε

2 1 2 2 2 1

exp exp . . . 2

DRAIN CURRENT

∫

=

d s

V V imref inv ds

d Q L W I φ µ GAUSS THEOREM

) (

2 1 s s si inv

E E Q − = ε

to calculate physical Ids, unknowns are ψs1 and ψs2

BOUNDARY CONDITIONS

) (

1 1 1 s g si

• x

s

V c E ψ ε − = ) (

2 2 2 s g si

• x

s

V c E ψ ε − − =

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2005 MODELING DIFFICULTIES

MATHEMATICAL DIFFICULTIES

FIRST DIFFICULTY DEFINE 2 CASES AND THEN UNIFY THEM ASYMMETRY Not always a minimum of potential in the silicon film: 2 CASES

Ψs1 Ψs2

i

Ψs1 Ψs2

Efermi

Ψs1 Ψs2 Ψs1 Ψs2

ψmin ψmin

Band diagrams

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2005 MODELING DIFFICULTIES

MATHEMATICAL DIFFICULTIES

2 OPTIONS SECOND DIFFICULTY NO EXACT SOLUTIONS OF ψs1 AND ψs2 4 unknown parameters,

ψs1Source, ψs1Drain & ψs2Source , ψs2Drain

FLOATING NODE RESOLUTION MAKE PHYSICAL ASSUMPTIONS Simplifications of Poisson equation

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2005 DIFFERENT KINDS OF MODELS

! 1st OPTION: IMPLICIT ANALYTICAL RESOLUTION Use of floating nodes or iterative resolutions to solve Poisson’s equation. ! 2nd OPTION: EXPLICIT ANALYTICAL RESOLUTION Poisson’s equation is solved with physical approximations allow to get explicit formulations of electrical parameters fully analytical model. – Charge-based model – Vth-based model

DIFFERENT WAYS OF MODELING

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2005 IMPLICIT ANALYTICAL MODELING

• MAIN ACTORS: 3 teams

– Y. Taur (USA, University of California): mainly for SDG MOSFET – M. Chan (Hong Kong University of Science & Technology): ADG MOSFET – T. Nakagawa (Japan, AIST): ADG MOSFET

!Y. Taur, “ Analytical Solutions of Charge and Capacitance in Symmetric and Asymmetric DG MOSFET”, IEEE Trans. Electron Devices, vol.48, n°12, Dec. 2001. !M. Chan, “Quasi-2D Compact Modeling for DG MOSFET”, NSTI Nanotech, vol.2, pp.108- 113, 2004. !Nakagawa et al., “ Improved Compact Modeling for Four-Terminal DG MOSFETs”, NSTI Nanotech, 2004.

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2005 IMPLICIT ANALYTICAL MODELING

WHY ?

COMPLEXITY of basic equations

ACCURACY because it keeps all basic equations without any (or with few) simplification PREDICTIVITY because basic equations could be solved for all materials and geometrical parameters No problem to unify the different operating modes

MANY ADVANTAGES

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2005 IMPLICIT ANALYTICAL MODELING

PRINCIPLE OF FLOATING NODE SOLUTION (Taur model)

2 different modes No minimum of potential Unknowns: ≈ ψS1 & ψS2 Minimum of potential Unknowns: ψ0 and x0 4 FLOATING NODES for each case SOURCE & DRAIN SIDE 2 UNKNOWNS + Each mode should be NUMERICALLY solved thanks to BOUNDARY CONDITIONS.

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2005 IMPLICIT ANALYTICAL MODELING

PRINCIPLE OF FLOATING NODE SOLUTION (Taur model)

DRAIN CURRENT Ids

∫

=

d s

V V imref inv ds

d Q L W I φ µ NUMERICALLY ANALYTICALLY (EKV METHOD)

d s

V V inv inv ds

Q Q I         − = 2 .

2

α Not really true for ADG because

• f interface coupling:

need a unification

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2005 IMPLICIT ANALYTICAL MODELING

PRINCIPLE OF FLOATING NODE SOLUTION (Taur model)

Symmetrical case: VerilogA + Eldo simulator Asymmetrical case: VerilogA + Eldo simulator Currently: convergence problem

SDG : L=0.5µm, W=1.0µm, Tsi=10.0nm, Tox=1.2nm

0.0 2.0 4.0 6.0 8.0 10.0 12.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 4.0 8.0 12.0 16.0

Gate Voltage (V) Transconductance (µS) Drain current (µA)

Vds =5mV

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.5 1.0 1.5 2.0 2.5

Transconductance Drain current ( mA)

Vgs =0.6 to 1.2V

Gate Voltage (V) (µS)

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2005 IMPLICIT ANALYTICAL MODELING

• LIMITS:
• Convergence problems

because of the 4 floating nodes.

• Simulation time.
• For that, we choose to developp an explicit

analytical model with only 1 floating node: T°

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2005 EXPLICIT ANALYTICAL MODELING

• MAIN ACTORS: 2 teams

– J. G. FOSSUM (USA, University of Florida) – G. Pei (USA, Cornell University)

• TWO KINDS OF EXPLICIT ANALYTICAL MODEL

– Charge-based model – Vth model

!

• J. G. Fossum et al., “UFDG and Nanoscale FinFET CMOS Design and Performance

Projections”, IEEE ICICT, 2005. ! A.V. Kammula et al., “ A long Channel Model for the Asymmetric DG MOSFET Valid in All Regions of Operation”, IEEE Southwest Symposium Mixed-Signal Design, pp.156-161, 2003. !

• G. Pei, “A Physical Compact Model of DG MOSFET for Mixed-Signal Circuit Applications –

Part1: Model Description”, IEEE Transac. On Electron Devices, vol.50, n°10, Oct. 2003.

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2005 EXPLICIT ANALYTICAL MODELING

ADVANTAGES OF AN EXPLICIT ANALYTICAL MODEL – Better physical understanding – Easier to use for circuit design because of speed and convergence whatever the number of transistors DISADVANTAGES OF AN EXPLICIT ANALYTICAL MODEL – Less accurate in moderate inversion – Difficulties to get well derivatives

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2005 EXPLICIT ANALYTICAL MODELING

• Weak inversion for both interfaces
• Strong inversion for both interfaces

CHARGE-BASED MODEL

1 2 2 2 1 1

2 ) 2 1 ( 2 ) 2 1 (

g

• x

si si g

• x

si si s g

• x

si si g

• x

si si s

V C C C V C C C V C C C V C C C + + + − = + + + − = ψ ψ Cox Cox Csi Vg1 ψs1 ψs2 Vg2

DG = capacitor divider

SI ds SI ds SI ds

I I I

2 1 +

=

Both channels are independent

Tsi Silicon film Volume current

Volume inversion

Tsi

Silicon film Surface current

Ids1

SI

Ids2

SI

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2005 EXPLICIT ANALYTICAL MODELING

One interface is in strong inversion and the other one in weak inversion.

Second integration

• f Poisson’s equation

Boundary conditions

WI ds SI ds ds

I I I

2 1 +

=

Tsi Ids2

WI

Ids1

SI

Surface current Volume current

Asymptotic case : ψs1→ ∞ thus exp(-ψs1) →0 CHARGE-BASED MODEL

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2005 EXPLICIT ANALYTICAL MODELING

LIMITS: unification between different operating modes

10-13 10-11 10-9 10-7 10-5 0.1 0.3 0.5 0.7 0.9 1.1

Ids (A)

2.10-6 4.10-6 6.10-6

Model

Vg1 (Volt) Ids (A) Vg2 from 0.1 to 0.3 V

Atlas simulations

Vds = 5mV

5.10-04 1.10-03 2.10-03 0.2 0.4 0.6 0.8 1 1.2

Vds (V) Id s (A )

Atlas simulations Model

Vg1=1.2V Vg2=1.2V Vg1=1.2V Vg2=0.1V

Tsi=15nm L=0.5µm W=1µm

Vds unification

CURRENT

Vg unification Vth-based model is developping: charge and current model take into account interface coupling

CHARGE-BASED MODEL

3.10-06 4.10-06 5.10-06 6.10-06 7.10-06 8.10-06 9.10-06 1.10-05 0.2 0.4 0.6 0.8 1 1.2

Vg1 (V) Ids (A)

Atlas simulations Model

Vg2=1.2V Vds=5mV

! Unification problem when Vg2 is high. ! Problems to have a continuous transconductance

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2005 EXPLICIT ANALYTICAL MODELING

• ASSUMPTION: no current flows from a channel to the
• ther one (checked by TCAD simulations)
• PRINCIPLE: 1 DGMOS = 2 SGMOS in parallel

Qinv = Qinv1 + Qinv2 Ids= Ids1 + Ids2 + INTERFACE COUPLING DESCRIPTION + CORRECTION FACTOR DEFINITION to well describe strong inversion UNIFICATION OF THE DIFFERENT OPERATING MODES

Vth-BASED MODEL

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2005 EXPLICIT ANALYTICAL MODELING

Vth-BASED MODEL

( )

              −       − − − − =

t g g Si eq t g g Si eq t g th th

U V V C C U V V C C U n V n V V . 2 ' ' . 2 ' ' tanh ln . . ' . 1 '

1 2 1 2 1 2 1 10 1

( )

              −       − − − − =

t g g Si eq t g g Si eq t g th th

U V V C C U V V C C U n V n V V . 2 ' ' . 2 ' ' tanh ln . . ' . 1 '

1 2 1 2 2 1 2 20 2

FRONT & BACK Vth

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2005 EXPLICIT ANALYTICAL MODELING

INTERFACE COUPLING DESCRIPTION

( )

        − − − =

t imref th g t i WI inv

u n n V V u n q x Q . . exp . . .

1 1 1 1 1

φ

Vth-BASED MODEL

Example: front interface in weak inversion ) ( . 1

2 1 2 1

• x

si

• x
• x

si

C C C C C n + + =

( ) ( )

( )

( ) ( )

x x n V V C L W x Q

i imref i thi gi

• xi

invSI

ε φ µ − − − − = 1 . . ' ' .

CORRECTION FACTOR TO WELL DESCRIBE STRONG INVERSION

n1 represents interface coupling εi represents the dependance

• f the interface strong inverted

versus its gate voltage

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2005 EXPLICIT ANALYTICAL MODELING

UNIFICATION OF THE DIFFERENT OPERATING MODES

Vth-BASED MODEL

Vg unification Vds unification

1 1 1 1

• ff

th g gt

V V V V − − =

Strong inversion Weak inversion

            − − =

1 1 1 1 1 1

2 exp n u V V V n u V

t

• ff

th g t gt

                      − − +         − − + =

1 1 1 1 1 1 1 1 1

2 exp 2 1 2 exp 1 ln 2 n u V V n u V V V n u V

t th g t

• ff

th g t gt

( )

      + − − + − − − =

dsati ds dsati ds dsati dsati dsieff

V V V V V V V δ δ δ 4 2 1

2

Voff=ε1(Vg-Vth)

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2005 EXPLICIT ANALYTICAL MODELING

10-14 10-13 10-12 10-11 10-10 10-09 10-08 10-07 10-06 10-05 10-04 0.2 0.4 0.6 0.8 1 1.2

Vg1 (V) Ids (A)

Vg2 = 0.1 to 1.2V

Vds = 5mV Model Atlas simulations

1.10-4 2.10-4 3.10-4 4.10-4 5.10-4 6.10-4 7.10-4 0.2 0.4 0.6 0.8 1.0 1.2

Vds (V) Ids (A) Vg1=0.8 to 1.2V Vg2=1.2V

Atlas simulation Model

Vth-BASED MODEL

Ids (A)

5.10-5 10-4 1.5.10-4 2.10-4 2.5.10-4 0.2 0.4 0.6 0.8 1 1.2

Vds (V)

Vg1 = 0.8 to 1.2V

Vg2=0.1V Model Atlas simulations

Tsi=10nm L=0.5µm W=1µm

1.10-6 2.10-6 3.10-6 4.10-6 5.10-6 6.10-6 7.10-6 8.10-6 9.10-6 1.10-5 0.2 0.4 0.6 0.8 1 1.2

Vg1 (V) Ids (A) Vg2=0.1 to 1.2V Vds=5mV Atlas simulation Model

CURRENT Logarithmic scale Linear scale Linear scale Linear scale

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2005 EXPLICIT ANALYTICAL MODELING

Vth-BASED MODEL

• 1.2
• 0.8
• 0.4

0.0 0.4 0.8 1.2

Vds (V)

40 30 20 10 50 60

Cgs Cgd Cds

Vg1=1.2V Vg2=0.0V

Capacitance (fF)

Cgs

• 0.6

0.0 0.6 1.2

Vg1 (V) Cgd Cds

Vds=0.0V Vg2=0.0V 40 30 20 10

Capacitance (fF)

CAPACITANCE

Tsi=10nm L=0.5µm W=3.5µm

CHARGE MODELING CAPACITANCE

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2005 EXPLICIT ANALYTICAL MODELING

LIMITS

Vth-BASED MODEL

Tsi < 10nm: problem in derivative

Pink : numerical model Bleue : Vth model L=1µm, W=10µm Tsi = 5nm Vds=5mV 0.2 0.4 0.6 0.8 1.0 1.2 Vg (V) 20 40 60 80 Transconductance (µS)

ADG but SYMMETRICAL BEHAVIOR KINK

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2005 EXPLICIT ANALYTICAL MODELING

EXAMPLE OF SIMULATION CIRCUITS USING Vth MODEL IN VERILOG-A

INVERTORS CHAIN COMPOSED OF 8 TRANSISTORS ARE SIMULATED IN TRANSIENT REGIME The model took into account: !classical SCE (Vth(Vds)) !access resistance

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2005 CONCLUSION

Quantum effects

EFFECTS WHICH SHALL BE ADDED SUMMARY CHARGE-BASED OR Vt MODEL 2 MAIN WAYS TO MODEL ADG MOSFET: IMPLICIT ANALYTICAL MODEL: ITERATIVE RESOLUTION EXPLICIT ANALYTICAL MODEL: FULLY ANALYTICAL EXPRESSIONS

Accurate Short Channel Effects Ballistic transport

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2005