ARM Cortex-M4 Programming Model Logical and Shift Instructions - - PowerPoint PPT Presentation

ARM Cortex-M4 Programming Model Logical and Shift Instructions

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References: Textbook Chapter 4, Sections 4.1, 4.2, 4.3, 4.5, 4.6, 4.9 “ARM Cortex-M Users Manual”, Chapter 3

CPU instruction types

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 Data movement operations

 memory-to-register and register-to-memory

 includes different memory “addressing” options  “memory” includes peripheral function registers

 register-to-register  constant-to-register (or to memory in some CPUs)

 Arithmetic operations

 add/subtract/multiply/divide  multi-precision operations (more than 32 bits)

 Logical operations

 and/or/exclusive-or/complement (between operand bits)  shift/rotate  bit test/set/reset  compare

 Flow control operations

 branch to a location (conditionally or unconditionally)  branch to a subroutine/function  return from a subroutine/function

Bitwise Logic

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AND {Rd,} Rn, Op2 Bitwise logic AND. Rd ← Rn & operand2 ORR {Rd,} Rn, Op2 Bitwise logic OR. Rd ← Rn | operand2 EOR {Rd,} Rn, Op2 Bitwise logic exclusive OR. Rd ← Rn ^ operand2 ORN {Rd,} Rn, Op2 Bitwise logic NOT OR. Rd ← Rn | (NOT operand2) BIC {Rd,} Rn, Op2 Bit clear. Rd ← Rn & NOT operand2 BFC Rd, #lsb, #width Bit field clear. Rd[(width+lsb–1):lsb] ← 0 BFI Rd, Rn, #lsb, #width Bit field insert. Rd[(width+lsb–1):lsb] ← Rn[(width-1):0] MVN Rd, Op2 Move NOT, logically negate all bits. Rd ← 0xFFFFFFFF EOR Op2

Yifeng Zhu Lecture Slides

Bard, Gerstlauer, Valvano, Yerraballi

ARM Logic Operations

 Bit-Wise Logic Instructions

AND{S} {Rd,} Rn, <op2> ; Rd=Rn & op2 ORR{S} {Rd,} Rn, <op2> ; Rd=Rn | op2 EOR{S} {Rd,} Rn, <op2> ; Rd=Rn ^ op2 BIC{S} {Rd,} Rn, <op2> ; Rd=Rn & (~op2) (bit clear) ORN{S} {Rd,} Rn, <op2> ; Rd=Rn | (~op2) MVN{S} Rd, <op2> ; Rd=(~op2) (complement all bits)

A Rn B Operand2 A&B AND A|B ORR A^B EOR A&(~B) BIC A|(~B) ORN ~A MVN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bard, Gerstlauer, Valvano, Yerraballi

To set bits

Use the or operation to set selected bits of a register to 1. (The other bits remain constant.) Friendly software modifies just the bits that need to be. GPIO_PORTD_DIR_R |= 0x03; // Set PD1,PD0 outputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value ORR R1,R1,#0x03 ; set bits 0 and 1 STR R1,[R0] ; update c7 c6 c5 c4 c3 c2 c1 c0 value of R1

1 1

0x03 constant (“mask”) c7 c6 c5 c4 c3 c2 1 1 result of the ORR

Set a Bit (in C)

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a |= (1 << k) a = a | (1 << k)

• r

a7 a6 a5 a4 a3 a2 a1 a0 1 a7 a6 1 a4 a3 a2 a1 a0

Example: k = 5

a 1 << k a | (1 << k)

Bard, Gerstlauer, Valvano, Yerraballi

To clear bits

Use the and operation to clear selected bits of a register. GPIO_PORTD_DIR_R &= 0xFC; // PD1,PD0 inputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value AND R1,R1,#0xFC ; clear bits 0 and 1 STR R1,[R0] ; update c7 c6 c5 c4 c3 c2 c1 c0 value of R1

1 1 1 1 1 1

0xFC constant (“mask”) c7 c6 c5 c4 c3 c2 0 0 result of the AND

Clear a Bit (in C)

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a &= ~(1<<k) a = a & ~(1<<k)

a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 1 1 1 1 a7 a6 a4 a3 a2 a1 a0

Example: k = 5

a ~(1 << k) a & ~(1<<k) (1 << k)

Bard, Gerstlauer, Valvano, Yerraballi

Using BIC to clear bits

Use the bic operation to clear selected bits of a register. GPIO_PORTD_DIR_R &= ~0x03; // PD1,PD0 inputs Assembly: LDR R0,=GPIO_PORTD_DIR_R LDR R1,[R0] ; read previous value BIC R1,R1,#0x03 ; clear bits 0 and 1 STR R1,[R0] ; update c7 c6 c5 c4 c3 c2 c1 c0 value of R1

1 1 1 1 1 1 0 0

0x03 = ~0xFC = “mask” c7 c6 c5 c4 c3 c2 0 0 result of the AND

Similar to AND, but more “straightforward” - bits to be cleared are designated.

Bard, Gerstlauer, Valvano, Yerraballi

To toggle

The exclusive or operation can also be used to toggle bits. GPIO_PORTD_DATA_R ^= 0x80; /* toggle PD7 */ Assembly: LDR R0,=GPIO_PORTD_DATA_R LDR R1,[R0] ; read port D EOR R1,R1,#0x80 ; toggle bit 7 STR R1,[R0] ; update

b7 b6 b5 b4 b3 b2 b1 b0 value of R1

1 0 0 0 0 0 0 0

0x80 constant ~b7 b6 b5 b4 b3 b2 b1 b0 result of the EOR

Toggle a Bit (in C)

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a ^= 1<<k

a7 a6 a5 a4 A3 a2 a1 a0 1 a7 a6 NOT(a5) a4 a3 a2 a1 a0

Example: k = 5

a 1 << k a ^= 1<<k a5 1 a5⊕1 1 1 1 1 Truth table of Exclusive OR with one Without knowing the initial value, a bit can be toggled by XORing it with a “1”

Bard, Gerstlauer, Valvano, Yerraballi

Switch Interfacing

The and operation to extract, or mask, individual bits: Pressed = GPIO_PORTA; //true if PA6 switch pressed Assembly: LDR R0,=GPIO_PORTA LDRB R1,[R0] ; read port A ANDS R1,#0x40 ; clear all bits except bit 6 BNE SwitchSet ; branch if Switch pulled high a7 a6 a5 a4 a3 a2 a1 a0 value of R1

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0x40 constant

0 a6 0 0 0 0 0 0

result of the AND

Input port LM3S or TM4C +3.3V 10kΩ s Input port +3.3V 10kΩ t LM3S or TM4C Open Closed Not pressed Pressed Negative logic Positive logic Note: If 8-bit result is zero, then we know a6 = 0 If the 8-bit result is non-zero, then a6 = 1

Bard, Gerstlauer, Valvano, Yerraballi

Switch Interfacing

The TST operation to extract, or mask, individual bits: Pressed = GPIO_PORTA; //true if PA6 switch pressed Assembly: LDR R0,=GPIO_PORTA LDRB R1,[R0] ; read port A TST R1,#0x40 ; clear all bits except bit 6 BNE SwitchSet ; branch if Switch pulled high

• TST performs the ANDS operation, except that the left-

hand

• perand

(R1 above) remains unchanged –

• nly

the flags are set.

Input port LM3S or TM4C +3.3V 10kΩ s Input port +3.3V 10kΩ t LM3S or TM4C Open Closed Not pressed Pressed Negative logic Positive logic Note: If 8-bit result is zero, then we know a6 = 0 If the 8-bit result is non-zero, then a6 = 1

Bard, Gerstlauer, Valvano, Yerraballi

Shift Operations

31 30 29 28 27 26 1 C

LSR ASR LSL ROR RRX Logical Shift Right Arithmetic Shift Right Logical Shift Left Rotate Shift Right Rotate Right Extended 1<n<32 0<n<31 1<n<32 1<n<32 n=1

Formats: LSL Rd, Rm, # imm ; imm = # bit positions to shift (n) LSL Rd, Rm, Rs ; Rs = # bit positions to shift (n) Use the ASR instruction when manipulating signed numbers, and use the LSR instruction when shifting unsigned numbers

Barrel Shifter

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 Second ALU operand has a special hardware called Barrel shifter

 Shift a designated #bits left/right in one step

 Example:

ADD r1, r0, r0, LSL #3 ; r1 = r0 + r0 << 3 = 9 × r0

Bard, Gerstlauer, Valvano, Yerraballi

Shift Example

High and Low are unsigned 4-bit components, which will be combined into a single unsigned 8-bit Result. Result = (High<<4)|Low;

Assembly:

LDR R0,=High LDR R1,[R0] ; read value of High LSL R1,R1,#4 ; shift into position LDR R0,=Low LDR R2,[R0] ; read value of Low ORR R1,R1,R2 ; combine the two parts LDR R0,=Result STR R1,[R0] ; save the answer

h3 h2 h1 h0 value of High in R1 h3 h2 h1 h0 0 after last LSL l3 l2 l1 l0 value of Low in R2 h3 h2 h1 h0 l3 l2 l1 l0 result of the ORR instruction

Example: C statements

 C: z = (a << 2) | (b & 15);  Assembler:

LDR r4,=a ; get address for a LDR r0,[r4] ; get value of a LSL r0,r0,#2 ; perform shift LDR r4,=b ; get address for b LDR r1,[r4] ; get value of b AND r1,r1,#15 ; perform AND ORR r1,r0,r1 ; perform OR LDR r4,=z ; get address for z STR r1,[r4] ; store value for z

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