Architecture Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, - - PowerPoint PPT Presentation

Advanced Design Issues for OASIS Network-on-Chip Architecture

Kenichi Mori, Adam Esch, Abderazek Ben Abdallah, Kenichi Kuroda

The University of Aizu, Japan

2010/11/4 BWCCA 2010 1

Fifth International Conference on Broadband and Wireless Computing, Communication and Applications, Nov.4, 2010

Contents

• Background
• Original OASIS NoC

– Architecture – Drawback

• Our contribution
• Proposal designed ONoC mechanism

– Stall-go control flow methodology – ONoC(Optimized NoC) Architecture

• Simulation result
• Summary

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• Network-on-Chip can solve bus-based problem
• Scalable architectural platform with huge

potential to handle growing complexity

• Processing elements are connected via

a packet switched communication network

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Background

P1 P3 P2 P4 P6 P5

s s s s s s

P1 P3 P2 P4 P6 P5

Bus-based system Network-on-Chip system

P: Processing element S: Switch

OASIS NoC: Network

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• Original OASIS* NoC has

4x4 mesh network

• Each router has
• ne processing element

* A. Ben Abdallah, M.Sowa, Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization, JASSST2006, Dec. 4-9th, 2006.

OASIS whole network

OASIS NoC: Routing

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• Routing algorithm is

static XY routing

• Switching method is

worm hole

OASIS whole network Routing information source destination Flit structure

drop_in

Local Input_port

sw_alloc

crossbar

76

South Input_port North Input_port West Input_port East Input_port

5

port_req[24:0]

drop_out

cntrl[24:0]

5 5 5 5 5 16 16 16 16 16

data_in_L[379:0] data_in_S[379:0] data_in_N[379:0] data_in_W[379:0] data_in_E[379:0] data_out_L[379:0] data_out_S[379:0] data_out_W[379:0] data_out_N[379:0] data_out_E[379:0]

80 76 76 76 76 76 76 76 76 76

tail

data_out_L[0] data_out_S[0] data_out_N[0] data_out_W[0] data_out_E[0]

OASIS NoC: Router design

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One router has three pipeline stages

First stage: They have buffering and routing mechanisms Second stage: It has scheduling and flow control mechanism Third stage: It sends flits each adequate next port

OASIS NoC drawback

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• Original OASIS NoC has an overhead problem

– Large number of dropped flits in congestion communication

Router PE Router PE Dropped flits

Large overhead

Node should send again full

Congestion

Our contribution

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• Optimized NoC(ONoC) can overcome the

OASIS overhead problem

• To avoid dropped flits, an efficient stall-

go (ESG) algorithm is proposed

Contents

• Background
• Original OASIS NoC

– Architecture – Drawback

• Our contribution
• Proposal designed ONoC mechanism

– Stall-go control flow methodology – ONoC(Optimized NoC) Architecture

• Simulation result
• Summary

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Efficient stall-go (ESG) algorithm

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Out = 0 Nearly_full = 1 Data_sent = 0 Nearly_full = 1 Data_sent = 1 Out = 0 Out = 1 Nearly_full = 0 Data_sent = 1 Out = 0 Nearly_full = 1 Data_sent = 0 Out = 1 Nearly_full = 0 Data_sent = 0

Sent Stop Go

Mealy machine for ESG algorithm

ONoC: Architecture

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ESG

Scheduler nearly full

stop

1 1 20 data_out 20 data_in nearly full 1 20 data_in nearly full 1 20 20 20 20 20 1 20 1 1

ESG

Scheduler

1 20 20 1 1 1

data_sent

data_out 1 data_sent nearly full 1 1 1 block grant

stop

1 1 block grant

• ESG is implemented between input port and scheduler
• ESG receives nearly full and data sent signal
• If receiver FIFO will be full, stall go controls to

stop sending flits

ONoC: Router design

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Local Input_port

sw_alloc

crossbar

yaddr[2:0] 3 20 3

South Input_port

3 20 3

North Input_port

3 20 3

West Input_port

3 20 3

stop[4:0]

1 1 1 1 1

East Input_port

3 20 3 5

port_req[24:0] sw_req[4:0]

tail_sent[4:0] data_in[99:0]

cntrl[24:0]

xaddr[2:0] 1 1 1 1 1 20 20 20 20 20 5 5 5 5 5 1 1 1 1 1

data_in_L[19:0] data_in_S[19:0] data_in_N[19:0] data_in_W[19:0] data_in_E[19:0] data_out_L[19:0] data_out_S[19:0] data_out_W[19:0] data_out_N[19:0]

tail sent

data_out_L[0] data_out_S[0] data_out_N[0] data_out_W[0] data_out_E[0] data_out_E[19:0] data_out_L[5:1] data_out_S[5:1] data_out_N[5:1] data_out_W[5:1] data_out_E[5:1]

5

Nearly_full

ESG is implemented

Efficient stall-go achievement

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Router PE Router PE

full Just stop sending

Congestion

Flits are sent without overhead

Contents

• Background
• Original OASIS NoC

– Architecture – Drawback

• Our contribution
• Proposal designed ONoC mechanism

– Stall-go control flow methodology – ONoC(Optimized NoC) Architecture

• Simulation result
• Summary

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Simulation parameters

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ONoC parameters configurations Network size 3x3-mesh Buffer depth 4, 8, 16 and 32 Flit size 20 bit (Header: 12 bit Payload: 8 bit) Forwarding Wormhole switching Scheduling Round-robin Flow control Stall-go Routing static X-Y routing Target application JPEG codec Target device Altera Stratix III Input data size 120,015 bytes(ratio 200x200)

50000 100000 150000 200000 250000 4 8 16 32 OASIS cycles ONoC cycles

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Buffer depth cycles

ONoC total communication time is less than OASIS in small buffer depth

ONoC communication time analysis

ONoC complexity analysis

Buffer size Architecture Area (ALUTs) Power (mW) Speed (MHz) 4 ONoC 5,485(5%) 649.17 185.87 OASIS 5,282(5%) 649.03 207.90 8 ONoC 8,269(7%) 660.02 186.60 OASIS 7,890(7%) 659.31 195.05 16 ONoC 10,538(9%) 682.80 161.26 OASIS 10,279(9%) 681.63 177.43 32 ONoC 17,416 (15%) 716.87 153.96 OASIS 16,569 (15%) 716.02 172.38

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4.38 % extra hardware

Summary

• This research presents optimization technique

and architecture of a Optimized NoC

• ONoC achieves 14.18 % less communication

time than OASIS, and area is only 4.38 % larger than OASIS

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On going work

• Buffer borrowing algorithm
• Short cut bus

Thank you for listening

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