anne bracy cs 3410 computer science cornell university
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Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, S. McKee, E. Sirer, and H. Weatherspoon] How does a processor interact with its environment? Computer System = Memory + Datapath + Control + Input + Output


  1. Anne Bracy CS 3410 Computer Science Cornell University [K. Bala, A. Bracy, S. McKee, E. Sirer, and H. Weatherspoon]

  2. How does a processor interact with its environment? Computer System = Memory + Datapath + Control + Input + Output Network Keyboard Disk Display

  3. I/O connected with I/O Controllers high-performance interconnect: processor, memory, display lower-performance interconnect: disk, keyboard, network Core0 Core1 Cache Cache Bridge High Performance Lower Performance Interconnect Legacy Interconnect Memory I/O I/O I/O I/O Controller Controller Controller Controller Controller Memory Display Disk Keyboard Network

  4. Processor – Memory (“Front Side Bus”) • Short, fast, & wide • Mostly fixed topology, designed as a “chipset” – CPU + Caches + Interconnect + Memory Controller I/O and Peripheral busses (PCI, SCSI, …) • Longer, slower, & narrower • Flexible topology, multiple/varied connections • Interoperability standards for devices • Connect to processor-memory bus through a bridge

  5. Typical I/O Device API • a set of read-only or read/write registers Command registers • writing causes device to do something Status registers • reading indicates what device is doing, error codes, … Data registers • Write: transfer data to a device • Read: transfer data from a device Every device uses this API

  6. 1. Programmed I/O: special instructions talk over special busses Specify: device, data, direction • inb $a, 0x64 (keyboard status register) • outb $a, 0x60 (keyboard data register) • Protection: only allowed in kernel mode (expensive) 2. Memory-Mapped I/O: map registers into virtual address space • Accesses to certain addresses redirected to I/O devices • Data goes over the memory bus (faster!) • Protection: via bits in pagetable entries • OS+MMU+devices configure mappings

  7. Memory-Mapped I/O 0xFFFF FFFF I/O 0x00FF FFFF Controller Display Physical I/O Address Controller Virtual Space Disk Address agreed-upon Space I/O locations for Controller communication Keyboard I/O Controller Network 0x0000 0000 0x0000 0000 vs. less-favored alternative = Programmed I/O: Syscall instructions that communicate with I/O • Communicate via special device registers •

  8. Memory Mapped I/O Programmed I/O struct kbd { char read_kbd() char status, pad[3]; { char data, pad[3]; do { }; sleep(); kbd *k = mmap(...); status = inb(0x64); syscall } while(!(status & 1)); char read_kbd() { return inb(0x60); do { syscalls } sleep(); Clicker Question: Which is better? status = k->status; (A) Programmed I/O } while(!(status & 1)); (B) Memory Mapped I/O return k->data; (C) Both have syscalls, both are bad }

  9. How to talk to device? • Programmed I/O or Memory-Mapped I/O How to get events? • Polling or Interrupts How to transfer lots of data? disk->cmd = READ_4K_SECTOR; Very, disk->data = 12; Very, Expensive while (!(disk->status & 1) { } for (i = 0..4k) buf[i] = disk->data;

  10. 1. Programmed: Device ßà CPU ßà RAM Transfer for (i = 1 .. n) CPU RAM • CPU issues read request • Device puts data on bus & CPU reads into registers DISK • CPU writes data to memory 2. Direct Memory Access (DMA): Device ßà RAM • CPU sets up DMA request CPU RAM • for (i = 1 ... n) Device puts data on bus & RAM accepts it DISK • Device interrupts CPU after done

  11. Programmed I/O • Requires special instructions • Can require dedicated hardware interface to devices • Protection enforced via kernel mode access to instructions • Virtualization can be difficult Memory-Mapped I/O • Re-uses standard load/store instructions • Re-uses standard memory hardware interface • Protection enforced with normal memory protection scheme • Virtualization enabled with normal memory virtualization scheme

  12. How does program learn device is ready/done? 1. Polling: Periodically check I/O status register • Common in small, cheap, or real-time embedded systems � Predictable timing, inexpensive � Wastes CPU cycles 2. Interrupts: Device sends interrupt to CPU • Cause register identifies the interrupting device • Interrupt handler examines device, decides what to do � Only interrupt when device ready/done � Forced to save CPU context (PC, SP, registers, etc. ) � Unpredictable, event arrival depends on other devices’ activity Clicker Question: Which is better? (A) Polling (B) Interrupts (C) Both equally good/bad

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