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ad -heap: an Efficient Heap Data Structure for Asymmetric Multicore Processors Weifeng Liu and Brian Vinter Niels Bohr Institute University of Copenhagen Denmark { weifeng, vinter } @nbi.dk March 1, 2014 Weifeng Liu and Brian Vinter (NBI) ad

  1. ad -heap: an Efficient Heap Data Structure for Asymmetric Multicore Processors Weifeng Liu and Brian Vinter Niels Bohr Institute University of Copenhagen Denmark { weifeng, vinter } @nbi.dk March 1, 2014 Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 1 / 52

  2. First Section Heap Data Structure Review Binary heap Figure: The layout of a binary heap (2-heap) of size 12. Given a node at storage position i , its parent node is at ⌊ ( i − 1) / 2 ⌋ , its child nodes are at 2 i + 1 and 2 i + 2. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 2 / 52

  3. First Section Heap Data Structure Review d -heaps [Johnson, 1975] Figure: The layout of a 4-heap of size 12. For node i , its parent node is at ⌊ ( i − 1) / d ⌋ , its child nodes begin from di + 1 and end up at di + d . Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 3 / 52

  4. First Section Heap Data Structure Review Cache-aligned d -heaps [LaMarca and Ladner, 1996] Figure: The layout of a cache-aligned 4-heap of size 12. For node i , its parent node is at ⌊ ( i − 1) / d ⌋ + offset , its child nodes begin from di + 1 + offset and end up at di + d + offset , where offset = d − 1 is the padded head size. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 4 / 52

  5. First Section Heap Data Structure Review Operations on the d -heaps insert adds a new node at the end of the heap, increases the heap size to n + 1, and takes O ( log d n ) worst-case time to reconstruct the heap property, delete-max copies the last node to the position of the root node, decreases the heap size to n − 1, and takes O ( dlog d n ) worst-case time to reconstruct the heap property, update-key updates a node, keeps the heap size unchanged, and takes O ( dlog d n ) worst-case time to reconstruct the heap property. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 5 / 52

  6. First Section Heap Data Structure Review Update-key operation on the root node (step 0) Figure: Initial status. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 6 / 52

  7. First Section Heap Data Structure Review Update-key operation on the root node (step 1) Figure: Update the value of the root node. Then the heap property on the level-1 and level-2 might be broken. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 7 / 52

  8. First Section Heap Data Structure Review Update-key operation on the root node (step 2) Figure: Find the maximum child node of the updated parent node. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 8 / 52

  9. First Section Heap Data Structure Review Update-key operation on the root node (step 3) Figure: Compare, and swap if the max child node is larger than its parent node. Then the heap property on the level-2 and level-3 might be broken. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 9 / 52

  10. First Section Heap Data Structure Review Update-key operation on the root node (step 4) Figure: Find the maximum child node of the updated parent node. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 10 / 52

  11. First Section Heap Data Structure Review Update-key operation on the root node (step 5) Figure: Compare, and swap if the max child node is larger than its parent node. Then no more child node, heap property reconstruction is done. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 11 / 52

  12. First Section Heap Data Structure Review Update-key operation on the root node (step 6) Figure: Final status. Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 12 / 52

  13. First Section Heap Data Structure Review Unroll the above update-key operation Step 1: update the root node Step 2: find-maxchild Step 3: compare-and-swap Step 4: find-maxchild Step 5: compare-and-swap Step 6: heap property satisfied, return Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 13 / 52

  14. Second Section When Heaps Met GPUs Running d -heaps on GPUs? Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 14 / 52

  15. Second Section When Heaps Met GPUs The above update-key operation on GPUs Given a 32-heap running in a thread-block (or work-group) of size 32 threads (or work-items). Step 1: update the root node Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 15 / 52

  16. Second Section When Heaps Met GPUs The above update-key operation on GPUs Given a 32-heap running in a thread-block (or work-group) of size 32 threads (or work-items). Step 1: update the root node Step 2: find-maxchild (parallel reduction) Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 16 / 52

  17. Second Section When Heaps Met GPUs The above update-key operation on GPUs Given a 32-heap running in a thread-block (or work-group) of size 32 threads (or work-items). Step 1: update the root node Step 2: find-maxchild (parallel reduction) Step 3: compare-and-swap Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 17 / 52

  18. Second Section When Heaps Met GPUs The above update-key operation on GPUs Given a 32-heap running in a thread-block (or work-group) of size 32 threads (or work-items). Step 1: update the root node Step 2: find-maxchild (parallel reduction) Step 3: compare-and-swap Step 4: find-maxchild (parallel reduction) Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 18 / 52

  19. Second Section When Heaps Met GPUs The above update-key operation on GPUs Given a 32-heap running in a thread-block (or work-group) of size 32 threads (or work-items). Step 1: update the root node Step 2: find-maxchild (parallel reduction) Step 3: compare-and-swap Step 4: find-maxchild (parallel reduction) Step 5: compare-and-swap Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 19 / 52

  20. Second Section When Heaps Met GPUs The above update-key operation on GPUs Given a 32-heap running in a thread-block (or work-group) of size 32 threads (or work-items). Step 1: update the root node Step 2: find-maxchild (parallel reduction) Step 3: compare-and-swap Step 4: find-maxchild (parallel reduction) Step 5: compare-and-swap Step 6: heap property satisfied, return Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 20 / 52

  21. Second Section When Heaps Met GPUs Pros and Cons Pros – why we want GPUs? Run much faster find-maxchild using parallel reduction Load continuous child nodes with few memory transactions (coalesced memory access) Shallow heap can accelerate insert operation Cons – why we hate them? Run slow compare-and-swap using only one single weak thread Other threads have to wait for a long time due to single-thread high-latency off-chip memory access Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 21 / 52

  22. Third Section Asymmetric Multicore Processors Emerging Asymmetric Multicore Processors (AMPs) Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 22 / 52

  23. Third Section Asymmetric Multicore Processors The block diagram of an AMP used in this work The chip consists of four major parts: a group of Latency Compute Units (LCUs) with caches, a group of Throughput Compute Units (TCUs) with shared command processors, scratchpad memory and caches, a shared memory management unit, and a shared global DRAM Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 23 / 52

  24. Third Section Asymmetric Multicore Processors Heterogeneous System Architecture (HSA): a step forward Main features in the current HSA design: the two types of compute units share unified memory address space no data transfer through PCIe link large pageable memory for the TCUs much more efficient LCU-TCU interactions due to coherency fast LCU-TCU synchronization mechanism user-mode queueing system shared memory signal object much lighter driver overhead Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 24 / 52

  25. Third Section Asymmetric Multicore Processors Leveraging the AMPs? A direct way is to exploit task, data and pipeline parallelism in the two types of cores. But, we still have two questions: Whether or not the AMPs can expose fine-grained parallelism in fundamental data structure and algorithm design? Can new designs outperform their conventional counterparts plus the coarse-grained (task, data and pipeline) parallelization? Weifeng Liu and Brian Vinter (NBI) ad -heap ( GPGPU-7 , Salt Lake City) March 1, 2014 25 / 52

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