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A Topology-Aware Performance Monitoring Tool for Shared Resource Management in Multicore Systems TADaaM Team - Nicolas Denoyelle - Brice Goglin - Emmanuel Jeannot August 24, 2015 1. Context/Motivations 2. Fast presentation of the tool 3.

  1. A Topology-Aware Performance Monitoring Tool for Shared Resource Management in Multicore Systems TADaaM Team - Nicolas Denoyelle - Brice Goglin - Emmanuel Jeannot August 24, 2015

  2. 1. Context/Motivations 2. Fast presentation of the tool 3. Demonstration 4. How does it works ? 5. How is it made ? 6. Features & Future Works TADaaM Team - Nicolas Denoyelle - Brice Goglin - Emmanuel Jeannot August 24, 2015

  3. MOTIVATIONS IO Memory hierarchy is growing deeper Network and larger. Machine No performance without a fair usage of the NUMA NUMA system topology Shared Memory Shared Memory Batch schedulers, runtimes, Shared Cache Shared Cache applications Private Cache Private Cache Private Cache Private Cache themeselves . . . are getting Core Core Core Core topology aware. Processing Unit PU PU PU PU PU PU PU Topology Aware Performance Monitoring August 24, 2015- 3

  4. MOTIVATIONS IO Memory hierarchy is growing deeper Network and larger. Machine Hence, data management gives NUMA NUMA opportunities for performance Shared Memory Shared Memory improvements. Shared Cache Shared Cache Private Cache Private Cache Private Cache Private Cache Core Core Core Core Processing Unit PU PU PU PU PU PU PU Topology Aware Performance Monitoring August 24, 2015- 4

  5. MOTIVATIONS IO Memory hierarchy is growing deeper Network and larger. Machine Hence, data management gives NUMA NUMA opportunities for performance Shared Memory Shared Memory improvements. Shared Cache Shared Cache Private Cache Private Cache Private Cache Private Cache Core Core Core Core Processing Unit PU PU PU PU PU PU PU Topology Aware Performance Monitoring August 24, 2015- 4

  6. MOTIVATIONS IO Memory hierarchy is growing deeper Network and larger. Machine Hence, data management gives NUMA NUMA opportunities for performance Shared Memory Shared Memory improvements. Shared Cache Shared Cache It is a multi-level and Private Cache Private Cache Private Cache Private Cache a multi-criteria problem. Core Core Core Core Processing Unit PU PU PU PU PU PU PU Topology Aware Performance Monitoring August 24, 2015- 4

  7. MOTIVATIONS • Need to match use cases, and relevant performance metrics for each level. • Need to match performance and topology. • Requires topology modeling skills. • Requires adaptable performance monitoring. Topology Aware Performance Monitoring August 24, 2015- 5

  8. Yet Another Tool to Monitor Applications Performance • Focus on data presentation to link the results with topology informations. • Relies on two cornerstones of topology modeling (hwloc) and performance counter abstraction (PAPI) to map the latter on the former • Minimal configuration and software requirements. • Can help finding and caracterizing localized bottlenecks. Topology Aware Performance Monitoring August 24, 2015- 6

  9. Hardware Locality (hwloc) Portable abstraction of hierarchical architectures for high-performance computing • Performs topology discovery and extracts hardware component information. • Provides tools for memory and process binding. • Many operating systems supported • ... • lstopo utility to display the topology: Developped at Inria Bordeaux. Topology Aware Performance Monitoring August 24, 2015- 7

  10. Hardware Locality (hwloc) Machine (31GB total) NUMANode P#0 (31GB) Package P#0 L3 (20MB) L2 (256KB) L2 (256KB) L2 (256KB) L2 (256KB) L2 (256KB) L2 (256KB) L2 (256KB) L2 (256KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) Core P#0 Core P#1 Core P#2 Core P#3 Core P#4 Core P#5 Core P#6 Core P#7 PU P#0 PU P#2 PU P#4 PU P#6 PU P#8 PU P#10 PU P#12 PU P#14 PU P#16 PU P#18 PU P#20 PU P#22 PU P#24 PU P#26 PU P#28 PU P#30 Topology Aware Performance Monitoring August 24, 2015- 7

  11. Performance Application Programming Interface (PAPI) Consistent interface and methodology for use of the performance counter hardware. • Real time relation between software performance and processor events. • Many operating systems supported too. • Reliable and actively supported. • Used in a wide range of performance analysis applications. An abstraction layer to plug some other performance library is under development. Topology Aware Performance Monitoring August 24, 2015- 8

  12. Dynamic Lstopo (example) Machine (16GB total) NUMANode P#0 (16GB) Package P#0 L3 (20MB) 9,8000000000e+01 2,5900000e+02 L2 (256KB) L2 (256KB) 2,2400000e+02 2,7600000e+02 L2 (256KB) 2,4000000e+02 L2 (256KB) 2,4000000e+02 L2 (256KB) 5,0700000e+02 L2 (256KB) 2,1900000e+02 L2 (256KB) 3,0100000e+02 L2 (256KB) L1d (32KB) 6,5800000e+02 L1d (32KB) 6,8200000e+02 L1d (32KB) 6,8700000e+02 L1d (32KB) 6,8700000e+02 7,2600000e+02 L1d (32KB) L1d (32KB) 1,0560000e+03 6,4200000e+02 L1d (32KB) L1d (32KB) 6,8200000e+02 L1i (32KB) 1,7140000e+03 L1i (32KB) 1,7350000e+03 1,7220000e+03 L1i (32KB) 1,7380000e+03 L1i (32KB) 1,7670000e+03 L1i (32KB) 2,3410000e+03 L1i (32KB) 1,7440000e+03 L1i (32KB) 1,7130000e+03 L1i (32KB) Core P#0 Core P#1 Core P#2 Core P#3 Core P#4 Core P#5 Core P#6 Core P#7 PU P#0 2,82176e+00 2,45916e+00 PU P#2 2,68772e+00 PU P#4 1,51689e+00 PU P#6 PU P#8 1,63417e+00 3,47249e+00 PU P#10 1,47808e+00 PU P#12 PU P#14 1,51514e+00 1,40868e+00 PU P#16 PU P#18 1,47441e+00 PU P#20 1,52142e+00 2,64271e+00 PU P#22 PU P#24 2,82472e+00 PU P#26 1,47165e+00 PU P#28 2,58947e+00 PU P#30 2,49344e+00 Sample of hardware performance counters mapped on a single socket of an Intel Xeon E5-2650 CPU. Topology Aware Performance Monitoring August 24, 2015- 9

  13. A Demonstration Worth Thousand Words L1 L2 L3 PU3 PU2 PU1 PU0 . . . ∗ 4 Accesses to a linked list of variable size. Topology Aware Performance Monitoring August 24, 2015- 10

  14. A Demonstration Worth Thousand Words L1 L2 L3 PU3 PU2 PU1 PU0 . . . ∗ 4 Accesses to a linked list of variable size. Topology Aware Performance Monitoring August 24, 2015- 10

  15. A Demonstration Worth Thousand Words L1 L2 L3 PU3 PU2 PU1 PU0 . . . ∗ 4 Accesses to a linked list of variable size. Topology Aware Performance Monitoring August 24, 2015- 10

  16. A Demonstration Worth Thousand Words L3_MISS{ L1_MISS{ OBJ = L3; OBJ = L1d; CTR = PAPI_L3_TCM; CTR = PAPI_L1_DCM; LOGSCALE = 1; LOGSCALE = 1; } } L2_MISS{ SINGLE_L3_MISS{ OBJ = L2; OBJ = PU; CTR = PAPI_L2_TCM; CTR = PAPI_L3_TCM; LOGSCALE = 1; LOGSCALE = 1; } } Topology Aware Performance Monitoring August 24, 2015- 11

  17. Dynamic Lstopo (Usage) Counters input: Machine (16GB total) NUMANode P#0 (16GB) SINGLE L3 MISS { OBJ = L3 ; Package P#0 CTR = L3 (4096KB) 2,5120000000e+03 PAPI L2 TCM/PAPI L2 TCA ; LOGSCALE = 1; L2 (256KB) L2 (256KB) L2 (256KB) L2 (256KB) MAX=1000000; MIN=0; L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) L1d (32KB) } L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) L1i (32KB) Core P#0 Core P#0 Core P#0 Core P#0 Core P#0 Core P#1 Core P#1 Core P#1 Core P#1 Core P#1 Command line: PU P#0 PU P#0 PU P#0 PU P#0 PU P#0 PU P#0 PU P#1 PU P#1 PU P#1 PU P#1 PU P#1 PU P#1 PU P#2 PU P#2 PU P#2 PU P#2 PU P#2 PU P#2 PU P#3 PU P#3 PU P#3 PU P#3 PU P#3 PU P#3 lstopo –perf-input counters input Topology Aware Performance Monitoring August 24, 2015- 12

  18. Dynamic Lstopo (Theory) 1. Spawn one pthread per L2 hardware thread (PU#0, . . . , PU#3). + L1 L1 + + PU PU PU PU Topology Aware Performance Monitoring August 24, 2015- 13

  19. Dynamic Lstopo (Theory) 1. Spawn one pthread per L2 hardware thread (PU#0, . . . , PU#3). 2. For each timestamp, each + L1 L1 thread collects a local set of performance counters. + + PU PU PU PU Topology Aware Performance Monitoring August 24, 2015- 13

  20. Dynamic Lstopo (Theory) 1. Spawn one pthread per L2 hardware thread (PU#0, . . . , PU#3). 2. For each timestamp, each + L1 L1 thread collects a local set of performance counters. 3. Counters are accumulated in + + PU PU PU PU each upper level. Topology Aware Performance Monitoring August 24, 2015- 13

  21. Dynamic Lstopo (Theory) 1. Spawn one pthread per L2 % hardware thread (PU#0, . . . , PU#3). 2. For each timestamp, each % L1 + L1 % thread collects a local set of performance counters. 3. Counters are accumulated in + + % PU PU % % PU PU % each upper level. 4. For each level, a leaf computes an arithmetic expression of the performance counters in the set. Topology Aware Performance Monitoring August 24, 2015- 13

  22. Dynamic Lstopo Software Architecture in Brief lstopo utility Monitors output Application monitors library hwloc library PAPI library Machine static topology Machine dynamic performance counters Topology Aware Performance Monitoring August 24, 2015- 14

  23. Dynamic Lstopo Software Architecture in Brief lstopo utility Monitors output Application monitors library hwloc library PAPI library Machine static topology Machine dynamic performance counters Topology Aware Performance Monitoring August 24, 2015- 14

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