A Sub-pA Current Sensing Front-End for Transient Induced Molecular - PowerPoint PPT Presentation

A Sub-pA Current Sensing Front-End for Transient Induced Molecular Spectroscopy Da Ying, Ping-Wei Chen, Chi-Yang Tseng, Yu-Hwa Lo, and Drew A. Hall University of California, San Diego, CA, USA Symposia on VLSI Technology and Circuits

New Drug Discovery • High-cost (>$2.6B/drug 1 ) and failure rate from mid- to late-stage • Many diseases are highly linked to protein-ligand abnormality [1] Need a solution for accurate in-vitro study of protein-ligand interactions [1] Pharmaceutical Research and Manufacturers of America Symposia on VLSI Technology and Circuits Slide 1

Existing Methods for Protein-Ligand Detection Surface Plasmon Resonance FRET [1] [2] ü Binding kinetics ü Solution phase û Immobilization of ligand û Labelling of ligand Labeling and immobilization significantly limit degree of freedom for binding [1] J. Homola, Analytical and Bioanalytical Chemistry , 2003; [2] C. Fan, TRENDS in Biotechnology , 2005 Symposia on VLSI Technology and Circuits Slide 2

Transient Induced Molecular Spectroscopy (TIMES) 𝐽 = 𝜖𝑅 𝜖𝑢 ü Label- and immobilization-free in-vitro protein-ligand detection ü Closer to physiological conditions and better signal integrity Requires a sensitive AFE for charge sensing T. Zhang, Y. Lo, Scientific Reports , 2016 Symposia on VLSI Technology and Circuits Slide 3

µTIMES Specification Parameter Application Circuit Sensor size 8 channels 300µm × 300µm M6 Resolution 0.1 µM sensitivity 100 fA Cross-scale DR 0.1 µM – 10 mM range 100 fA – 1 µA Bandwidth 5 cm/s flow rate 10 Hz • Active area < 0.2 mm 2 /ch. • Partition across 4 references with 80dB SNDR each • WE/RE à pseudo-differential input T. Zhang, Y. Lo, ACS Central Science , 2016 Symposia on VLSI Technology and Circuits Slide 4

Existing Sub-pA Current AFEs [H. Li, TBioCAS’16] [C. Hsu, ISSCC’18] û Sensitive to aliasing û Heavy digital backend û Input sampling à noise folding û Large area, limited # of channels û Charge injection to sensor Aim to achieve 100fA sensitivity with small area/power Symposia on VLSI Technology and Circuits Slide 5

Proposed µ TIMES AFE Architecture µTIMES à 1 st -order current-mode ΔΣ + digital IIR (linear predictor) ① 1-bit quantizer + digital IIR achieves quasi multi-bit quantization Symposia on VLSI Technology and Circuits Slide 6

Proposed µ TIMES AFE Architecture Integrator only needs to process half of original pulse amplitude ② Tri-level PWM avoids intensive hardware and relaxes filter linearity Symposia on VLSI Technology and Circuits Slide 7

Proposed µ TIMES AFE Architecture Lower 𝑔 ( relaxes speed requirement and improves anti-aliasing ③ Multi-bit feedback effectively reduces 𝑔 ' Symposia on VLSI Technology and Circuits Slide 8

Issues with Single-bit Quantization 𝑃𝑇𝑆 ,-./ • Limited SQNR for given OSR ∝ 2 3 45 4670 𝑃𝑇𝑆 0-./ • Deterministic quantization noise 𝑜 = Quantizer bits • Arbitrary quantizer gain 𝑀 = order Limited SQNR à Large OSR à Power hungry & poor anti-aliasing Symposia on VLSI Technology and Circuits Slide 9

Issues with Single-bit Quantization • Limited SQNR for given OSR What we will find later: • Deterministic quantization noise More transitions and quantization levels à less tonal effect • Arbitrary quantizer gain Deterministic quantization noise à tonal à SNR ò Symposia on VLSI Technology and Circuits Slide 10

Issues with Single-bit Quantization • Limited SQNR for given OSR • Deterministic quantization noise • Arbitrary quantizer gain Arbitrary quantizer gain à deviate from linear model Symposia on VLSI Technology and Circuits Slide 11

Motivation: Linear Prediction in ΔΣ 𝑦 n + 1 = 𝑦 n + 𝜖𝑦 𝜖𝑢 > ∆𝑈 = 𝑦 n + 𝑦 n − 𝑦[n − 1] 𝑬 𝐩𝐯𝐮 n = 𝐸 IJ/ n − 1 + 2×𝑅 IJ/ n − 𝑅 IJ/ [n − 1] 43P RS L MNO [P] Q MNO [P] = IIR filter à 03P RS à Multi-bit achieved with only a 4-bit adder, scaler, and two FFs Symposia on VLSI Technology and Circuits Slide 12

Turning 1-bit Into Multi-bit First-order observations: • D out closely tracks input signal • More transitions à less tonal • Quantization step ∈ {∆, 3∆} • 𝑔 (.Y,Z[\ and PSD? Symposia on VLSI Technology and Circuits Slide 13

Theoretical PSD and 𝒈 (.Y,Z[\ Conservative SQNR analysis: à 𝑓 _ ∈ [− `∆ 4 , + `∆ 4 ] c∆ g∆ d 4 = d 𝑣 4 𝑒𝑣 = 0 à 𝜏 _ `∆ ∫ 3 c∆ 04 d ~9.5dB worse SQNR than ideal 4b Q 𝑔 (.Y,Z[\ requirement: hi (.,(4kl mno p7q) ≤ `∆ à hp t m 5vw `l `l à 𝑔 m m (.Y ≤ 4k>4 uRS 0xk IIR- ΔΣ requires OSR > 8 Symposia on VLSI Technology and Circuits Slide 14

STF & NTF 𝑂𝑈𝐺(𝑨) = (2 − 𝑨 30 )(1 − 𝑨 30 ) 0 |4kl (2 − 𝑓 3|4kl )(1 − 𝑓 3|4kl ) à 𝑇𝑈𝐺 𝑔 = • 1 st -order shaping NTF • ~9dB larger out-of-band gain Unity in-band STF & inherent anti-aliasing Symposia on VLSI Technology and Circuits Slide 15

IIR Quantizer Gain 2 − 𝑨 30 1 − 𝑨 30 𝑂𝑈𝐺 ‚ 𝑨 = 1 + 𝑙 > 𝑀 𝑨 𝑂𝑈𝐺 ‚ (𝑨) : NTF ( 𝑙 ≠ 1 ) 𝑀 𝑨 : loop gain ( 𝑙 = 1 ) 4 between quantizer input 𝑧 and output 𝑤 • 𝑙 - smallest 𝜏 ~ – 𝑙 = 𝑤, 𝑧 / 𝑧, 𝑧 [1] • Peak SNDR @ 0.8FS input level à define non-overloading range [0, 0.8FS] 𝑙 shows IIR quantizer can be statistically approximated as a multi-bit quantizer [1] S. Pavan, R. Schreier, G. Temes, ‘Understanding delta-sigma data converters’, John Wiley & Sons , 2017 Symposia on VLSI Technology and Circuits Slide 16

Tri-Level PWM DAC • PWM DAC – Entirely digital coded à less hardware – CT loop filter à pulse shape independent • Current-steering DAC – nA ~ µA reference from current-splitting – No loading à larger loop gain, linearity ñ • Two-level PWM à Tri-level PWM – Lose inherent linearity – Even-order distortion eliminated [1] – RZ DAC à ISI immunity – Half pulse à noise, jitter, OTA linearity ñ [1] F. Colodro, A. Torralba, TCAS-I , 2009 Symposia on VLSI Technology and Circuits Slide 17

Tri-Level PWM DAC Current steering Resistive 𝑇 .,Ž• 𝑔 = 4𝑙𝑈𝛿 2𝐽 Œ•Ž 𝑇 .,“ 𝑔 = 4𝑙𝑈 𝐽 Œ•Ž 𝑊 ŒŒ /2 𝑊 ŒŒ /2 • Current-steering DAC with shunt path – Bypass most noise for small input – Low-pass filtered bias noise – Linearity maintained by careful sizing • Lower jitter sensitivity 0 – 𝑇𝑂𝑆 „.//…† ∝ d d ‡ ˆ‰Š ‡ ‹ 4 – Half pulse amplitude à 𝜏 Œ•Ž ò 4x PWM ADC à Light weight, multi-bit Symposia on VLSI Technology and Circuits Slide 18

Current-Splitting DAC C. Enz, E. Vittoz, ISCAS , 1996 Symposia on VLSI Technology and Circuits Slide 19

Continuous-Time CMFB L. Luh, J. Draper, TCAS-II , 2000 Symposia on VLSI Technology and Circuits Slide 20

Chip Micrograph CMFB Bias 7% 22% W DAC µ 5 . 16% 11µW 3 8µW 28µW Integrator 55% Total power: 50.3µW/ch * Comparator and digital logic consumes negligible power Symposia on VLSI Technology and Circuits Slide 21

Measurement Results Input-referred current noise PSD Peak SNDR Capacitive loading à noise ñ 123fA sensitivity at 1nA reference Symposia on VLSI Technology and Circuits Slide 22

Measurement Results SNDR vs. input amplitude 78.2dB fixed-scale dynamic range Symposia on VLSI Technology and Circuits Slide 23

Measurement Results DC input sweep 139dB cross-scale dynamic range Symposia on VLSI Technology and Circuits Slide 24

TIMES In-vitro Measurement Setup PDMS cross-section Power supply To inlets 3 mm FPGA power µTIMES & microfluidic FPGA USB ENIG sensors Symposia on VLSI Technology and Circuits Slide 25

In-vitro Protein-Ligand Measurement Characteristic shape due to unique dipole moment and charge locality Symposia on VLSI Technology and Circuits Slide 26

Performance Summary Stana ć evi ć Li Sim Hsu Nazari This Work TBCAS’07 TBCAS’16 TBCAS’17 ISSCC’18 TBCAS’13 Hourglass CC + AFE Architecture Inc. ΔΣ Inc. ΔΣ ΔΣ IIR- ΔΣ ΔΣ SS ADC Process [ µ m] 0.5 0.5 0.35 0.18 0.35 0.18 Max Input [ µ A] 1 16 2.8 10 0.35 1.1 Resolution [fA] 100 100 100,000 100 24,000 123 @ BW [Hz] @ 0.1 @ 1 @ 10 @ 1.8 @ 100 @ 10 Conversion Time 8,388 1,000 4 400 10 100 @ Min. Input [ms] Input-referred - - 6,960 58.9 1,850 30.3 Noise [fA/ √ Hz] Fixed-/cross- 40* / 54.0* / 60.7 / 78.2 / 77.5 160 scale DR [dB] 140 164 95 139 On-chip Sensors? NO NO NO NO YES YES Num. of Channels 16 50 1 1 192 8 Area/ch. [mm 2 ] 0.25* 0.157 0.5 0.2 † 0.04 0.11 Power/ch. [ µ W] 3.4 ‡ 241 16.8 295 188 50.3 * estimated from figures; † not including synthesized digital area and DEM; ‡ off-chip bias Symposia on VLSI Technology and Circuits Slide 27