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A Study on Accelerated Built-in Self Test of Multi-Gb/s High Speed Interfaces Seong-Won Kang Samsung electronics/Sungkyunkwan University Department of Semiconductor Display Engineering 1 Seong-Won Kang Seong-Won Kang Mixed Signal Lab, SKKU

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Seong-Won Kang Mixed Signal Lab, SKKU Seong-Won Kang Mixed Signal Lab, SKKU

A Study on Accelerated Built-in Self Test of Multi-Gb/s High Speed Interfaces

Seong-Won Kang Samsung electronics/Sungkyunkwan University Department of Semiconductor Display Engineering

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Seong-Won Kang Mixed Signal Lab, SKKU

Contents

1. Introduction 2. Test architecture 3. Stereographic BER test 4. BER modeling 5. Accelerated test 6. Conclusion

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Seong-Won Kang Mixed Signal Lab, SKKU

  • 1. Introduction

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  • 1. Noise budgeting and Noise immunity

Important factor to analysis the performance of the high speed serial interfaces.

  • 2. BER and Eye-diagram measurement using the scope

BERT

DUT

PATTERN GENERATOR OSCILLOSCOPE

Probe s real input ≠observed signal

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Seong-Won Kang Mixed Signal Lab, SKKU

Contents

1. Introduction 2. Test architecture 3. Stereographic BER test 4. BER modeling 5. Accelerated test 6. Conclusion

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Seong-Won Kang Mixed Signal Lab, SKKU

  • 1. Proposed BIST architecture

I2C interface Tx with offset controllers, Rx with data aligner PRBS generator, PRBS verifier BIST logic with a bit error counter and a comparator

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  • 1. Test architecture

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test_en

sdata sclk I/O PRBS Gen.

15 1312 10

I2C TX

V-offset T-offset

BIST Logic

1

Comp. RX

Data Aligner

PRBS Ver.

13 12 10 15

16 16 Error Counter 16 16 16

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Seong-Won Kang Mixed Signal Lab, SKKU

Contents

1. Introduction 2. Test architecture 3. Stereographic BER test 4. BER modeling 5. Accelerated test 6. Conclusion

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Seong-Won Kang Mixed Signal Lab, SKKU

  • 15
  • 10
  • 5
  • 1

Timing offset [ps] Voltage offset [mV]

BER

Voltage offset [mV] Voltage offset [mV]

  • 1. Stereographic BER test sequence

Intentionally generate timing offset (Δt) voltage offset (ΔV)

  • Starts from the center of timing offset-axis
  • BER measurement is repeated over all the voltage offset values
  • BER test rerun with the next timing offset along all the voltage offset range
  • BER data is collected over all points in the Δt-ΔV plane
  • Color codes are assigned according to BER level
  • A full 2-dimensional stereographic BER diagram

à Visualize the timing and voltage margins of the interface circuit under test

10-15 @ 1Gbps 106 seconds 10-6 @ 4.8Gbs 0.2 m seconds

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  • 3. Stereographic BER test
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Seong-Won Kang Mixed Signal Lab, SKKU

Contents

1. Introduction 2. Test architecture 3. Stereographic BER test 4. BER modeling 5. Accelerated test 6. Conclusion

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Seong-Won Kang Mixed Signal Lab, SKKU

  • 1. Relationship between data sampling points and PDF

Ideally, the data are always sampled in the mid-bit. For out-of -band jitter cause bit errors Signal edge transition is distributed by RJ RJ is assumed to be Gaussian

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  • 4. BER modeling

Example of the jitter profile

Distributed by Random jitter

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Seong-Won Kang Mixed Signal Lab, SKKU

  • 2. BER modeling

The probability density function of a zero-mean Gaussian variable is where σ is the standard deviation. Assuming the uniform bit distribution, the BER can be expressed (the probability of bit transition is 50% when each error occurs)

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  • 4. BER modeling

2 2

2

2 1 ) (

δ

π δ

x

e x p

−

=

∫ ∫

∞ Δ Δ ∞ −

+ =

t t

dt t right P dt t left P BER ) ) ( _ ) ( _ ( * 5 . ) 2 1 2 1 ( * 5 .

2 2 2 2

2 ) ( 2

dt e dt e

UI t t t t δ δ

π δ π δ

− − Δ ∞ − − ∞ Δ

∫ ∫

+ =

dt e

t t

2 2

2

2 1

δ

π δ

− ∞ Δ∫

=

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Seong-Won Kang Mixed Signal Lab, SKKU

Integral of the Gaussian function turns into complementary error function. Complementary error function can be approximated to another Gaussian function for small Δt/ σ Simplified equation is where both A and B are constants.

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  • 4. BER modeling

B t A BER Log + Δ =

2 10

) ( | ) ( |

CDF (Cumulative distribution function) for the Gaussian distributions Gaussian distributions

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Seong-Won Kang Mixed Signal Lab, SKKU

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  • 4. BER modeling

Cross-section view of the stereographic BER diagram Curve fitting of the timing offset and BER

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Seong-Won Kang Mixed Signal Lab, SKKU

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  • 4. BER modeling

[6] LVDS Owner’s Manual, Fourth Edition, national.com/LVDS, pp.58, Fig. 6-13, 2008. [7] Michael Nelson, Pavel Zivny, “Impact of Noise on BER estimation”, Tektronix, August 2005.

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Seong-Won Kang Mixed Signal Lab, SKKU

Contents

1. Introduction 2. Test architecture 3. Stereographic BER test 4. BER modeling 5. Accelerated test 6. Conclusion

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Seong-Won Kang Mixed Signal Lab, SKKU

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  • 5. Accelerated test

Timing offset (UI) BER

1/8 1/4 3/8 1/2

  • 1/2
  • 3/8
  • 1/4
  • 1/8

10-6 10-1 10-2 10-3 10-15 1/8 1/4 3/8 1/2

  • 1/2
  • 3/8
  • 1/4
  • 1/8

1/√|Log10(BER)|

0.2 0.4 0.6 0.8 1 ① ②

③ ④

10-9

START

  • ffset = offset + LSB(Δt)

measure_count = measure_count + 1 BER(measure_count) = BER Report BER(0:3) and offset(0:3) END

  • ffset =
  • ffset - Δtmax/2n
  • ffset =
  • ffset + Δtmax/2n

N Y N Y Y

measure _count < 3

N

BER < 10-6 10-7< BER <= 10-6

  • ffset = Δtmax/2

n=0 n = n+1 Measure_count=0 BER(measure count) = BER

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Seong-Won Kang Mixed Signal Lab, SKKU

Contents

1. Introduction 2. Test architecture 3. Stereographic BER test 4. BER modeling 5. Accelerated test 6. Conclusion

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Seong-Won Kang Mixed Signal Lab, SKKU

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  • 6. Conclusion

Implemented the BIST logic. à à Examine the t, V margins using the stereographic BER diagram. Using the bit error model, à à Linear relationship between and timing margin Suggest the sequence of accelerated measurement using the linear fitting . The entire test is completed within 8~9 measurements for BER of 10-8 to 1 0-9. à à The BER test down to 10-15 at 1Gbps can be finished within 150msec. Under the these circumstance, I will keep finding more precisely modeling .

( ) |

| 1

10 BER

Log

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Seong-Won Kang Mixed Signal Lab, SKKU

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References

[1] Dongwoo Hong et al., “Bit Error Estimation for High Speed Serial Links,” IEEE Journal of Solid State Circuits, vol. 39, No. 9, pp. 1571-1580, September 2004. [2] Stefan Erb and Wolfgang Pribyl, “An Accurate and Efficient Method for BER Analysis in High-Speed Communication Systems”, IEEE European Conference on Circuit Theory and Design, August 2009. [3] Jung-Hoon Chun, “High speed interface circuit design and test schemes for memory systems”, Korea Information and Communications Society, December 2008. [4] Minchul Shin, Jongjoo Shim and Jaemin Kim, “A 6.4Gbps On-chip Eye Opening Monitor Circuit for Signal Integrity Analysis of High Speed Channel”, IEEE International Symposium of EMC, August 2008. [5] Stevan M. Berber, “An Automated Method for BER Characteristics Measurement”, IEEE Instrumentation and Measurement,

  • vol. 53, No. 2, pp. 575-580, April 2004.

[6] LVDS Owner’s Manual, Fourth Edition, national.com/LVDS, pp.58, Fig. 6-13, 2008. [7] Michael Nelson, Pavel Zivny, “Impact of Noise on BER estimation”, Tektronix, August 2005. [8] Leens, F., “An Introduction to I2C and SPI protocols”, IEEE Instrumentation and Measurement, vol. 12, No. 1, pp. 8-13, February 2009. [9] Wendemagegnehu T. Beyene et al., “Advanced modeling and accurate characterization of a 16 Gb/s memory interface,” IEEE

  • Trans. on Advanced Packaging, vol. 32, No. 2, pp. 437-659, May 2009.

[10] Yongquan Fan, “Accelerating Jitter and BER Qualifications of High Speed Seril Communication Interfaces”, Ph.D. Thesis, McGill University, February 2010. [11] Y. Cai, S. Werner, G. Zhang, M. Olsen, and R. Brink, “Jitter Testing for Multigigabit Backplane SerDes – Techniques to Decompose and Combine Various Types of Jitter,” Proceedings of IEEE International Test Conference, 2002, p700-709

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Seong-Won Kang Mixed Signal Lab, SKKU

Q & A

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