A Low-Latency Multi-Version Key-Value Store Using B-tree on an - - PowerPoint PPT Presentation

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A Low-Latency Multi-Version Key-Value Store Using B-tree on an - - PowerPoint PPT Presentation

May 03, 2023 354 likes •497 views

A Low-Latency Multi-Version Key-Value Store Using B-tree on an FPGA-CPU Platform Yuchen Ren , Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang State Key Laboratory of ASIC and System, Fudan University Bowei Yu, Hua Chen, Xianjun He,

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A Low-Latency Multi-Version Key-Value Store Using B-tree

  • n an FPGA-CPU Platform

Yuchen Ren, Jinyu Xie, Yunhui Qiu, Hankun Lv, Wenbo Yin, Lingli Wang

State Key Laboratory of ASIC and System, Fudan University

Bowei Yu, Hua Chen, Xianjun He, Zhijian Liao, Xiaozhong Shi

IT R&D Dept., Chengdu Research Institute, Huawei Technologies Co., Ltd. FPL’19, Barcelona, September 11th, 2019

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Introduction - Background

Multi-Version KVS

(Key-Value Store) CPU-based RDMA-based FPGA-based

low (power) efficiency

  • f CPU-centric

memory hierarchy limited flexibility and efficiency of RDMA

performance & power consumption

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*RDMA: Remote Direct Memory Access

Key Version1 Version2 Version... Value1 Value2 Value...

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Design

  • a low-latency multi-version in-memory KVS
  • FPGA-CPU heterogeneous architecture

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Introduction - Contribution

Storage

  • keys

– hash table – FPGA board (Cuckoo hashing)

  • version-value pairs (VVPs) –

B-trees – host memory

Operation

  • get, put, delete, CAS, getPredecessor –

bypassing the CPU

  • range query –

with the help of the CPU

*CAS: Compare and Swap

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Architecture

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Architecture - Network Offload Engine

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Architecture - Key-Value Store Engine

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Architecture - First-level indexing by key

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Architecture - Second-level indexing by version

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Xilinx KCU105

PC

2GB DDR4 two 10GbE PCIe gen3 x8

  • Intel i5-2400

quad-core CPU

  • 12GB DDR3
  • 256GB SSD
  • CentOS 7
  • FPGA platform
  • Xilinx KCU105
  • Frequency
  • KVSE: 120MHz
  • DMA: 250MHz
  • DDR4: 300MHz
  • NOE: 156.25MHz

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Implementation

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Evaluation - Key-Value Store Message Generator in FPGA hardware

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* Kops: Thousand operations per second

  • Latency increases almost linearly
  • KVSE is the bottleneck

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Evaluation - Results

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Comparison (latency, get operation)

  • Our KVS: < 8μs (within a B-tree of 5 levels )
  • Hybrid FPGA approach: ≈ 75μs (within a B+-tree of 5 levels )
  • Many software-based KVS systems: > 1ms (on the support of versioning)

Conclusion

Future work

  • Optimize the system architecture of our multi-version KVS.
  • Expand to a distributed KVS by setting up multiple storage hosts.

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* Hybrid FPGA approach: D. Heinrich, S. Werner, M. Stelzner, C. Blochwitz, T. Pionteck and S. Groppe, “Hybrid FPGA approach for a B+ tree in a semantic Web database system,” 2015 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Bremen, 2015, pp. 1-8.

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SLIDE 13

Thanks!

Contact

ycren18@fudan.edu.cn wbyin@fudan.edu.cn llwang@fudan.edu.cn