[PPT] - A 60GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD Teerachot PowerPoint Presentation

SLIDE 1

A 60GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD

Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan

2014 Asia-Pacific Microwave Conference 2014/11/6

SLIDE 2

1 Outline

Background
Issues and Previous Work
Proposed 60GHz Frequency

Synthesizer

–System Architecture –20GHz-to-5GHz Dual-Step-Mixing ILFD

Experimental Results
Conclusions

2014/11/6

SLIDE 3

2 Requirements for 60GHz PLLs

Out-of-band phase noise<-90dBc/Hz @1MHz to support 16QAM*
In-band phase noise should be lowered depending on the

bandwidth of carrier-recovery circuitry**

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20GHz PLL 60GHz I 60GHz Q 60GHz I 60GHz Q VGA LPF ADC VGA LPF ADC Digital BB RF front-end Analog/Digital BB Digital BB DAC DAC LPF LPF 60GHz 60GHz RX TX *,** K. Okada, et al., JSSC 2013

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3 Issues of mm-wave PLLs

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LPF ÷2 2 CM CML ÷(27,28, 29,30) ÷5 PFD CP 60GHz QILO

36MHz 2

20GHz VCO 58.32GHz, 60.48GHz, 62.64Ghz, 64.80GHz ÷2 2 CM CML

24.7mW 8mW 23mW 14mW

Low out-of-band phase noise by Injection Locking
96dBc/Hz at 1MHz at 61.56GHz
Large power consumption (64mW for 20GHz)
Does not support channel bonding and all standards

– Lower REF clk. required to support all standards (N )

SLIDE 5

4 PLL Noise Transfer Function

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 Divide ratio N is no longer contribute to CP/PFD output noise → Useful in a system with large division ratio N

For CP Noise;

X.Gao, et al., JSSC 2009

(G(s) is open-loop transfer function)

iCP,n Φout Kd 1 1+G(s) G(s)

iCP,n Φout Kd N 1+G(s) G(s)

PFD Charge Pump Loop Filter VCO

α 2π ICP H(f)

Kvco jf 1 N

Divider

[Φref] ΦVCO,n [Φout] iCP,n Φref,n

SLIDE 6

5 Proposed 60GHz Frequency Synthesizer

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LPF ÷4 ILFD ÷(54, 55,56,57, 58,59,60) ÷5 PFD with DZ CP2 ÷4.5 60GHz QILO

36MHz/ 40MHz REF

Sub-sampling Loop Frequency Locked Loop (En=1)/ Phase Locked Loop (En=0)

3 MUX1 SEL1

CP1 ÷2 20GHz Class-C VCO SSPD Pulser

En

58.32GHz, 59.40GHz, 60.48GHz, 61.56GHz, 62.64GHz, 63.72GHz, 64.80GHz

Var MUX3 MUX2 SEL3 SEL2

T. Siriburanon, et. al, RFIC 2014

SLIDE 7

6 20GHz PFD/CP PLL

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LPF ÷4 4 IL ILFD ÷(54, 55,56,57, 58,59,60) ÷5 PFD with DZ CP2 ÷4.5

36MHz/ 40MHz REF 3 MUX1 SEL1

CP1 ÷2 20GHz Class-C VCO SSPD Pulser

En Var MUX3 MUX2 SEL3 SEL2

Frequency Locked Loop (En=1)/ Phase Locked Loop (En=0)

PFD and CP2 are enabled

19.44GHz, 19.80GHz, 20.16GHz, 20.52GHz, 20.88GHz, 21.24GHz, 21.60GHz

NCP~1200

SLIDE 8

7 20GHz Sub-sampling PLL

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LPF ÷4 4 IL ILFD ÷(54, 55,56,57, 58,59,60) ÷5 PFD with DZ CP2 ÷4.5

36MHz/ 40MHz REF

Sub-sampling Loop

3 MUX1 SEL1

CP1 ÷2 20GHz Class-C VCO SSPD Pulser

En Var MUX3 MUX2 SEL3 SEL2

Frequency Locked Loop (En=1)/ Phase Locked Loop (En=0)

19.44GHz, 19.80GHz, 20.16GHz, 20.52GHz, 20.88GHz, 21.24GHz, 21.60GHz

Dead zone in PFD, SSPD and CP1 are enabled

Nss~20

SLIDE 9

8 20GHz SS-PLL Noise Modelling

140
120
100
80
60
40

1K 10K 100K 1M 10M

Phase noise (dBc/Hz) Frequency (Hz)

REF_Noise SSPD+CP+ LF noise VCO noise SSPLL PFD/CP PLL

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SLIDE 10

9 High-speed Divider Chains

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 A technique to increase locking range of high-

rder-division in ILFDs is necessary

 Large power  Locking range mismatch  Narrow locking range

3 ILFD 2 ILFD Digital Dividers

15GHz 5GHz 30GHz

Digital Dividers

5GHz 30GHz

6 ILFD 60GHz 5GHz ÷4 ILFD 20GHz ÷4 ILFD

SLIDE 11

10

Conv. Single-Step Injection ILFD

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0o 180o 45o 225o 90o 270o 135o 315o

+INJ Icore Icore Icore Icore +A (fo @ 0o)

A (fo @ 180o)

SLIDE 12

11

Conv. Single-Step Injection ILFD

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2π

Disturbing injection in grey Constructive injection in black time time time ILFD output (fo) Input (2fo) (direct divide-by-2) Input (4fo) (direct divide-by-4)

2π 4π +A

A

SLIDE 13

12 Dual-Step Injection ILFD

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0o 180o 45o 225o 90o 270o 135o 315o

2fo @ 0o 2fo @ 90o 2fo @ 180o 2fo @ 270o +INJ (+4fo) Icore Icore Icore Icore a b c d +A

A
B

+B +C

C
D

+D

INJ

(-4fo)

T. Siriburanon, et. al, ESSCIRC 2013

SLIDE 14

13 Dual-Step Injection ILFD

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Only constructive injections exist

. . . .

ILFD output (+fo,-fo) Common node signal (+2fo,-2fo)

+A -B +C

D

. . . . . . . . . . . . π 3π 2π 4π 5π π 2π

+INJ (+4fo)

INJ

(-4fo)

a b c d

time time time

SLIDE 15

14 Measured Locking Range

Can cover required range for 60GHz

Applications (19-22GHz)

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18
18
16
16
14
14
12
12
10
10
8
8
6
6
4
4
2
2

17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25

Injec ecti tion

n Power [dBm]

Injec ecti tion

n Frequenc

ency [GHz]

2.1 .1mW 2.4 .45mW 2.6 .65mW

SLIDE 16

15 ILFD Performance Comparison

Features Div. Ratio Locking Range* (GHz) Locking Range* (%) Power (mW) Area (mm2) [1] Direct mixing 4 22.6-28 21 8.3 0.140 [2] Direct mixing 4 6.0-7.6 22 6.8 0.007 [3] Direct mixing 4 31.0-41.0 27 3.3 0.002 [4] LC Direct mixing (3rd harmonic boosting) 4 58.5-72.9 21.9 2.2 0.032 [5] CML + LC ILFD 4 13.5-30.5 77.3 7.3 0.33 [6] Dual-Step Mixing 4 13.4-21.3 31 3.9 0.003 This Work Dual-Step Mixing 4 19-24.2 24 2.65 (with buffers) 0.002

[1] A-SSCC’07 [2] RFIC’04 [3] ISSCC’06 [4] CICC’12 [5] MTT’11 [6] A-SSCC’11

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SLIDE 17

16 20GHz SS-PLL Measurement

Freq. (GHz)

19.38 - 22.58(15.3%) Frequencies (GHz) 19.44, 19.80, 20.16, 20.52, 20.88, 21.24, 21.60

Ref. Spurs (dBc)
58 dBc @ fREF

PN@1MHz(dBc/Hz) ~ -104

Ref. freq. (MHz)

36/40 (18/20) Out Power (dBm) 0 ~ -4 Total Power (mW) 20.2 Process 65nm CMOS

20GHz SS-PLL

20GHz ILFD

CP1 SSPD

CP2

Digital Circuits PFD+DZ

Loop Filter

20GHz Class-C LC-VCO 20GHz Buffer

0.7 mm 0.8 mm

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SLIDE 18

17 Schematic of 60GHz QILO

60GHz Quadrature Injection-Locked Oscillator

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K. Okada, et al., JSSC 2013

SLIDE 19

18 60GHz QILO Measurement Summary

ILO Buffer ILO Buffer ILO Core

I+ I- Q+ Q- INJ+ INJ-

0.6 mm 1.0 mm Process 65nm CMOS Supply Voltage (V) 1.2 Tuning Range (GHz) 58.3-65.4 PDC (mW) 14.0 Output Power (dBm)

10.0

60GHz QILO

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SLIDE 20

19 Phase Noise Characteristics

At a carrier frequency of 62.64GHz

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SLIDE 21

20 Performance Comparison

Ref. REF Freq. (MHz) Frequency (GHz) Phase Noise @10kHz

ffset

Phase Noise @10MHz

ffset

Features Power (mW) [1] 100 57.0-66.0

66 dBc/Hz
108 dBc/Hz

Direct 60GHz QPLL 78 [2] 203.2 59.6-64.0

65 dBc/Hz
112 dBc/Hz

30GHz PLL + Coupler 76 [3] 100 56.0-62.0

71 dBc/Hz
109 dBc/Hz

60GHz AD-PLL 48 [4] 40 53.8-63.3

89 dBc/Hz
108 dBc/Hz

60GHz SS-QPLL 42 [5] 18 58.1-65.0

40 dBc/Hz
117 dBc/Hz

Sub-harmonic Injection 20GHz PLL + 60GHz QILO 72 This Work (normal) 18/20 58.3-65.4

40 dBc/Hz
115 dBc/Hz

Sub-harmonic Injection 20GHz PLL + 60GHz QILO 32.8 This (SS) 18/20 58.3-65.4

69 dBc/Hz
115 dBc/Hz

Sub-harmonic Injection 20GHz SS-PLL + 60GHz QILO 34.2

[1] K. Scheir, et al., ISSCC 2009 [2] C. Marcu, et al., JSSC 2009 [3] W. Wu, et al., ISSCC 2013 [4] V. Szortyka, et al., ISSCC 2014 [5] W. Deng, et al., JSSC 2013

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SLIDE 22

21 Conclusion

Low in-band and out-band phase noise have

been achieved through sub-sampling and sub-harmonic injection-locked techniques, respectively

With an assist of a low-power Dual-Step-

Mixing ILFD, the proposed 60GHz SS-PLL achieves low power consumption while maintaining good phase noise performance

2014/11/6