A 60GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD Teerachot - PowerPoint PPT Presentation

A 60GHz Sub-Sampling PLL Using A Dual-Step-Mixing ILFD Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, and Akira Matsuzawa Tokyo Institute of Technology, Japan 2014 Asia-Pacific Microwave Conference 2014/11/6

Outline 1 • Background • Issues and Previous Work • Proposed 60GHz Frequency Synthesizer – System Architecture – 20GHz-to-5GHz Dual-Step-Mixing ILFD • Experimental Results • Conclusions 2014/11/6

Requirements for 60GHz PLLs 2 Analog/Digital BB RF front-end 60GHz I VGA ADC 60GHz LPF Digital BB RX VGA ADC LPF 60GHz Q 20GHz PLL 60GHz I LPF DAC 60GHz Digital BB TX LPF DAC 60GHz Q • Out-of-band phase noise<-90dBc/Hz @1MHz to support 16QAM* • In-band phase noise should be lowered depending on the bandwidth of carrier-recovery circuitry** *,** K. Okada, et al ., JSSC 2013 2014/11/6

Issues of mm-wave PLLs 3 20GHz 60GHz QILO VCO 8mW 23mW 36MHz PFD CP LPF 24.7mW 2 58.32GHz, 60.48GHz, ÷ (27,28, ÷ 2 2 ÷ 2 2 ÷ 5 62.64Ghz, 64.80GHz CML CM CM CML 29,30) 14mW • Low out-of-band phase noise by Injection Locking • -96dBc/Hz at 1MHz at 61.56GHz • Large power consumption (64mW for 20GHz) • Does not support channel bonding and all standards – Lower REF clk. required to support all standards (N ) 2014/11/6

PLL Noise Transfer Function 4 Φ ref,n i CP,n Φ VCO,n [ Φ ref ] [ Φ out ] α K vco I CP H (f) 2 π jf Loop Charge VCO PFD Filter Pump 1 N Divider For CP Noise; 1 G ( s ) Φ out N G ( s ) Φ out i CP,n K d 1+ G ( s ) i CP,n K d 1+ G ( s ) (G(s) is open-loop transfer function)  Divide ratio N is no longer contribute to CP/PFD output noise → Useful in a system with large division ratio N X.Gao, et al., JSSC 2009 2014/11/6

5 Proposed 60GHz Frequency Synthesizer Sub-sampling Loop SEL 2 MUX 2 Pulser 20GHz ÷ 2 Class-C VCO 60GHz QILO 36MHz/ SSPD 40MHz CP 1 LPF REF SEL 3 PFD MUX 3 CP 2 with DZ 58.32GHz, 59.40GHz, 60.48GHz, SEL 1 E n Var 3 61.56GHz, ÷ (54, ÷ 4.5 62.64GHz, MUX 1 55,56,57, 63.72GHz, ÷ 4 ILFD ÷ 5 58,59,60) 64.80GHz Frequency Locked Loop ( E n =1)/ Phase Locked Loop ( E n =0) T. Siriburanon, et. al, RFIC 2014 2014/11/6

20GHz PFD/CP PLL 6 SEL 2 MUX 2 Pulser 20GHz ÷ 2 Class-C VCO 36MHz/ SSPD 19.44GHz, 40MHz CP 1 LPF REF 19.80GHz, 20.16GHz, 20.52GHz, SEL 3 PFD 20.88GHz, MUX 3 CP 2 with DZ 21.24GHz, 21.60GHz SEL 1 E n Var 3 ÷ (54, ÷ 4.5 MUX 1 55,56,57, N CP ~1200 ÷ 4 4 IL ILFD ÷ 5 58,59,60) Frequency Locked Loop ( E n =1)/ Phase Locked Loop ( E n =0) • PFD and CP 2 are enabled 2014/11/6

20GHz Sub-sampling PLL 7 Sub-sampling Loop SEL 2 MUX 2 Pulser 20GHz ÷ 2 Class-C VCO 36MHz/ SSPD 19.44GHz, 40MHz CP 1 LPF REF 19.80GHz, 20.16GHz, 20.52GHz, SEL 3 PFD 20.88GHz, MUX 3 CP 2 with DZ 21.24GHz, 21.60GHz SEL 1 E n Var 3 ÷ (54, ÷ 4.5 MUX 1 N ss ~20 55,56,57, ÷ 4 4 IL ILFD ÷ 5 58,59,60) Frequency Locked Loop ( E n =1)/ Phase Locked Loop ( E n =0) • Dead zone in PFD, SSPD and CP 1 are enabled 2014/11/6

20GHz SS-PLL Noise Modelling 8 REF_Noise -40 SSPD+CP+ Phase noise (dBc/Hz) LF noise VCO noise -60 SSPLL PFD/CP -80 PLL -100 -120 -140 1K 10K 100K 1M 10M Frequency (Hz) 2014/11/6

High-speed Divider Chains 9  Large power 60GHz 5GHz 30GHz 15GHz 5GHz ÷ 4 2 3 Digital  Locking range ILFD ILFD Dividers ILFD mismatch 30GHz 5GHz 20GHz  Narrow locking 6 ÷ 4 Digital ILFD ILFD Dividers range  A technique to increase locking range of high- order-division in ILFDs is necessary 2014/11/6

Conv. Single-Step Injection ILFD 10 +A ( f o @ 0 o ) 0 o 45 o 90 o 135 o +INJ 180 o 225 o 270 o 315 o -A ( f o @ 180 o ) I core I core I core I core 2014/11/6

Conv. Single-Step Injection ILFD 11 +A -A ILFD output ( f o ) time 2 π 0 Input (2 f o ) (direct divide-by-2) time 2 π 4 π 0 Input (4 f o ) (direct divide-by-4) time Disturbing injection in grey Constructive injection in black 2014/11/6

Dual-Step Injection ILFD 12 0 o 45 o 90 o 135 o -B +C -D +A -C +D -A +B 180 o 225 o 270 o 315 o 2 f o @ 0 o 2 f o @ 90 o 2 f o @ 180 o 2 f o @ 270 o b d c a -INJ +INJ (-4 f o ) (+4 f o ) I core I core I core I core T. Siriburanon, et. al, ESSCIRC 2013 2014/11/6

Dual-Step Injection ILFD 13 +A -B +C -D ILFD output . . . . . . . . . . . . . . . . (+ f o ,-f o ) time π 2 π 0 a b c d Common node signal (+2 f o ,-2 f o ) time 5 π π 2 π 3 π 4 π 0 +INJ (+4 f o ) time -INJ (-4 f o ) Only constructive injections exist 2014/11/6

Measured Locking Range 14 • Can cover required range for 60GHz Applications (19-22GHz) 0 -2 -2 on Power [dBm] -4 -4 -6 -6 -8 -8 -10 -10 tion 2.1 .1mW -12 -12 ecti 2.4 .45mW Injec -14 -14 2.6 .65mW -16 -16 -18 -18 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 Injec ecti tion on Frequenc ency [GHz] 2014/11/6

ILFD Performance Comparison 15 Locking Locking Div. Power Area Features Range* Range* Ratio (mW) (mm 2 ) (GHz) (%) [1] Direct mixing 4 22.6-28 21 8.3 0.140 [2] Direct mixing 4 6.0-7.6 22 6.8 0.007 [3] Direct mixing 4 31.0-41.0 27 3.3 0.002 LC Direct mixing (3 rd harmonic [4] 4 58.5-72.9 21.9 2.2 0.032 boosting) [5] CML + LC ILFD 4 13.5-30.5 77.3 7.3 0.33 [6] Dual-Step Mixing 4 13.4-21.3 31 3.9 0.003 This 2.65 Dual-Step Mixing 4 19-24.2 24 0.002 Work (with buffers) [1] A- SSCC’07 [2] RFIC’04 [3] ISSCC’06 [4] CICC’12 [5] MTT’11 [6] A- SSCC’11 2014/11/6

20GHz SS-PLL Measurement 16 0.7 mm Freq. (GHz) 19.38 - 22.58(15.3%) 19.44, 19.80, 20.16, Frequencies (GHz) 20.52, 20.88, 21.24, 20GHz Buffer Digital 21.60 Circuits PFD+DZ Ref. Spurs (dBc) -58 dBc @ f REF 0.8 mm 20GHz ILFD CP1 SSPD PN@1MHz(dBc/Hz) ~ -104 CP2 Ref. freq. (MHz) 36/40 (18/20) Out Power (dBm) 0 ~ -4 20GHz Class-C LC-VCO Total Power (mW) 20.2 Loop Filter Process 65nm CMOS 20GHz SS-PLL 2014/11/6

Schematic of 60GHz QILO 17 K. Okada, et al. , JSSC 2013 60GHz Quadrature Injection-Locked Oscillator 2014/11/6

60GHz QILO Measurement Summary 18 0.6 mm Process 65nm CMOS I+ I- Supply Voltage 1.2 (V) ILO Buffer Tuning Range 58.3-65.4 1.0 mm INJ+ (GHz) ILO Core INJ- P DC (mW) 14.0 ILO Buffer Output Power -10.0 (dBm) Q+ Q- 60GHz QILO 2014/11/6

Phase Noise Characteristics 19 At a carrier frequency of 62.64GHz 2014/11/6

Performance Comparison 20 REF Phase Noise Phase Noise Frequency Power Ref. Freq. @10kHz @10MHz Features (GHz) (mW) (MHz) offset offset [1] 100 57.0-66.0 -66 dBc/Hz -108 dBc/Hz Direct 60GHz QPLL 78 [2] 203.2 59.6-64.0 -65 dBc/Hz -112 dBc/Hz 30GHz PLL + Coupler 76 [3] 100 56.0-62.0 -71 dBc/Hz -109 dBc/Hz 60GHz AD-PLL 48 [4] 40 53.8-63.3 -89 dBc/Hz -108 dBc/Hz 60GHz SS-QPLL 42 Sub-harmonic Injection [5] 18 58.1-65.0 -40 dBc/Hz -117 dBc/Hz 72 20GHz PLL + 60GHz QILO This Sub-harmonic Injection Work 18/20 58.3-65.4 -40 dBc/Hz -115 dBc/Hz 32.8 20GHz PLL + 60GHz QILO (normal) Sub-harmonic Injection This 18/20 58.3-65.4 -69 dBc/Hz -115 dBc/Hz 20GHz SS-PLL + 60GHz 34.2 (SS) QILO [1] K. Scheir, et al ., ISSCC 2009 [2] C. Marcu, et al ., JSSC 2009 [3] W. Wu, et al., ISSCC 2013 [4] V. Szortyka, et al. , ISSCC 2014 [5] W. Deng, et al., JSSC 2013 2014/11/6

Conclusion 21 • Low in-band and out-band phase noise have been achieved through sub-sampling and sub-harmonic injection-locked techniques, respectively • With an assist of a low-power Dual-Step- Mixing ILFD, the proposed 60GHz SS-PLL achieves low power consumption while maintaining good phase noise performance 2014/11/6