[537] Beyond Physical Memory Chapters 21-22 Tyler Harter 9/29/14 - - PowerPoint PPT Presentation

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[537] Beyond Physical Memory Chapters 21-22 Tyler Harter 9/29/14 - - PowerPoint PPT Presentation

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[537] Beyond Physical Memory Chapters 21-22 Tyler Harter 9/29/14 Problem 1: PT Size page directory PFN: 0101 PFN: 0110 PFN:1111 PFN valid PFN valid PFN valid PFN valid 0101 1 0000 1 1001 1

slide-1
SLIDE 1

[537] Beyond Physical Memory

Chapters 21-22 Tyler Harter 9/29/14

slide-2
SLIDE 2

Problem 1: PT Size

slide-3
SLIDE 3

PFN
 0101
 1111


0110 valid
 1
 1
 0
 1


page directory

PFN
 0000
 1010


valid
 1
 1
 0
 0


PFN: 0101

Problem 2 (worksheet)

  • assume 12-bit


virtual addrs

PFN
 1001


valid
 1
 0
 0
 0


PFN: 0110

PFN


1011
 valid
 0
 0
 0
 1


PFN:1111

slide-4
SLIDE 4
  • code

data Program Virtual Memory

slide-5
SLIDE 5
  • code

data Program Virtual Memory code
 data heap

  • stack

Process 1

create

slide-6
SLIDE 6
  • code

data Program code
 data heap

  • stack

Process 1

create what’s in code?

Virtual Memory

slide-7
SLIDE 7
  • data

Program

LibA LibB Prog LibC

create

  • 


data heap

  • stack

Process 1

LibA LibB Prog LibC

many large libraries, some

  • f which are rarely/never used

Virtual Memory

slide-8
SLIDE 8

How to avoid wasting physical pages to back rarely used virtual pages?

slide-9
SLIDE 9
  • data

Program

LibA LibB Prog LibC

  • 


data heap

  • stack

Process 1

LibA LibB Prog LibC

Virtual Memory Phys Memory

Prog LibC

slide-10
SLIDE 10
  • data

Program

LibA LibB Prog LibC

  • 


data heap

  • stack

Process 1

LibA LibB Prog LibC

Virtual Memory Phys Memory

Prog LibC

slide-11
SLIDE 11
  • data

Program

LibA LibB Prog LibC

  • 


data heap

  • stack

Process 1

LibA LibB Prog LibC

Virtual Memory Phys Memory

Prog LibC

access LibB

slide-12
SLIDE 12
  • data

Program

LibA Prog LibC

  • 


data heap

  • stack

Process 1

LibA LibB Prog LibC

Virtual Memory Phys Memory

Prog LibC

copy (or move) to RAM

LibB LibB

slide-13
SLIDE 13
  • data

Program

LibA Prog LibC

  • 


data heap

  • stack

Process 1

LibA LibB Prog LibC

Virtual Memory Phys Memory

Prog LibC

called “swapping”

  • r “paging” in

LibB LibB

slide-14
SLIDE 14

How to know where a page lives?

slide-15
SLIDE 15

Present Bit

PFN valid prot 10 1 r-x

  • 23

1 rw-

  • 28

1 rw- 4 1 rw-

slide-16
SLIDE 16

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

slide-17
SLIDE 17

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

slide-18
SLIDE 18

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

access

slide-19
SLIDE 19

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 15 1 rw- 1 4 1 rw- 1

  • Phys Memory

Disk

access

slide-20
SLIDE 20

What if no RAM is left?

slide-21
SLIDE 21

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • FULL

Phys Memory Disk

slide-22
SLIDE 22

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

access FULL

slide-23
SLIDE 23

FULL

Present Bit

PFN valid prot present 10 1 r-x 1

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

access evict

slide-24
SLIDE 24

Present Bit

PFN valid prot present 25 1 r-x

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

access evict

slide-25
SLIDE 25

Present Bit

PFN valid prot present 25 1 r-x

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

access evict

called “swapping”

  • r “paging” out
slide-26
SLIDE 26

Present Bit

PFN valid prot present 25 1 r-x

  • 23

1 rw- 28 1 rw- 4 1 rw- 1

  • Phys Memory

Disk

access

slide-27
SLIDE 27

Present Bit

PFN valid prot present 25 1 r-x

  • 23

1 rw- 10 1 rw- 1 4 1 rw- 1

  • Phys Memory

Disk

access

slide-28
SLIDE 28

Why not leave page on disk?

slide-29
SLIDE 29

Performance: RAM vs. Disk

How long does it take to access a 4-byte int? RAM: 5ns to 40ns per int (depending on TLB hit) Disk: 15ms per int

slide-30
SLIDE 30

Performance: RAM vs. Disk

How long does it take to access a 4-byte int? RAM: 5ns to 40ns per int (depending on TLB hit) Disk: 15ms per int


  • because of high fixed costs

  • reading 4KB of ints: 15us per int

  • reading many megabytes of ints: 30ns per int
slide-31
SLIDE 31

Average Memory Access Time (AMAT)

Hit% = portion of accesses that go straight to RAM Miss% = portion of accesses that go to disk first Tm = time for memory access Td = time for disk access

  • AMAT = (Hit% * Tm) + (Miss% * Td)
slide-32
SLIDE 32

Average Memory Access Time (AMAT)

Hit% = portion of accesses that go straight to RAM Miss% = portion of accesses that go to disk first Tm = time for memory access Td = time for disk access

  • AMAT = (Hit% * Tm) + (Miss% * Td)
  • Problem 3
slide-33
SLIDE 33

Who should do swapping? H/W or OS?

slide-34
SLIDE 34

H/W

A

20 40 60 80 Disk:

A B

CPU:

A A A

slide-35
SLIDE 35

OS

A

20 40 60 80 Disk:

A B

CPU:

A A A B B

slide-36
SLIDE 36

OS

A

20 40 60 80 Disk:

A B

CPU:

A A A B B

context switch to other process while swapping in

slide-37
SLIDE 37

Translation Steps

H/W: for each mem reference:
 
 extract VPN from VA
 check TLB for VPN
 TLB hit:
 build PA from PFN and offset
 fetch PA from memory
 TLB miss:
 fetch PTE
 if (!valid): exception [segfault]
 else if (!present): exception [page fault, or page miss]
 else: extract PFN, insert in TLB, retry

slide-38
SLIDE 38

Translation Steps

H/W: for each mem reference:
 
 extract VPN from VA
 check TLB for VPN
 TLB hit:
 build PA from PFN and offset
 fetch PA from memory
 TLB miss:
 fetch PTE
 if (!valid): exception [segfault]
 else if (!present): exception [page fault, or page miss]
 else: extract PFN, insert in TLB, retry

which steps are expensive?

slide-39
SLIDE 39

Translation Steps

H/W: for each mem reference:
 
 extract VPN from VA
 check TLB for VPN
 TLB hit:
 build PA from PFN and offset
 fetch PA from memory
 TLB miss:
 fetch PTE
 if (!valid): exception [segfault]
 else if (!present): exception [page fault, or page miss]
 else: extract PFN, insert in TLB, retry

which steps are expensive?

(cheap) (cheap) (cheap) (expensive) (expensive) (expensive) (cheap) (expensive)

slide-40
SLIDE 40

Translation Steps

H/W: for each mem reference:
 
 extract VPN from VA
 check TLB for VPN
 TLB hit:
 build PA from PFN and offset
 fetch PA from memory
 TLB miss:
 fetch PTE
 if (!valid): exception [segfault]
 else if (!present): exception [page fault, or page miss]
 else: extract PFN, insert in TLB, retry

which steps are expensive?

(cheap) (cheap) (cheap) (expensive) (expensive) (expensive) (cheap) (expensive)

slide-41
SLIDE 41

Page-Fault Handler (OS)

PFN = FindFreePage()
 if (PFN == -1)
 PFN = EvictPage()
 DiskRead(PTE.DiskAddr, PFN)
 PTE.present = 1
 PTE.PFN = PFN
 retry instruction

slide-42
SLIDE 42

Page-Fault Handler (OS)

PFN = FindFreePage()
 if (PFN == -1)
 PFN = EvictPage()
 DiskRead(PTE.DiskAddr, PFN)
 PTE.present = 1
 PTE.PFN = PFN
 retry instruction

which steps are expensive?

slide-43
SLIDE 43

Page-Fault Handler (OS)

PFN = FindFreePage()
 if (PFN == -1)
 PFN = EvictPage()
 DiskRead(PTE.DiskAddr, PFN)
 PTE.present = 1
 PTE.PFN = PFN
 retry instruction

which steps are expensive?

(cheap) (depends) (cheap) (expensive) (cheap) (cheap) (cheap)

slide-44
SLIDE 44

Page-Fault Handler (OS)

PFN = FindFreePage()
 if (PFN == -1)
 PFN = EvictPage()
 DiskRead(PTE.DiskAddr, PFN)
 PTE.present = 1
 PTE.PFN = PFN
 retry instruction

what to evict?
 what to read? (policy)

(cheap) (depends) (cheap) (expensive) (cheap) (cheap) (cheap)

slide-45
SLIDE 45

Caching Policy

Workload: series of loads/stores to virtual pages Cache: chooses what to prefetch/evict Metric: hit rate, AMAT Cache “algebra”, given 2 variables, find the 3rd:

f(W, C) = M

slide-46
SLIDE 46

Cache

Upon access, we must load the desired page. Do we prefetch other adjacent pages?
 (remember disks have high fixed costs) Prefetching more means we will have to evict more. What to evict?

slide-47
SLIDE 47

Workload: is prefetching good?

time address … Spatial Locality time address … Temporal Locality

slide-48
SLIDE 48

Cache

Upon access, we must load the desired page. Do we prefetch other adjacent pages?
 (remember disks have high fixed costs) Prefetching more means we will have to evict more. What to evict?

slide-49
SLIDE 49

Cache

Upon access, we must load the desired page. Do we prefetch other adjacent pages?
 (remember disks have high fixed costs) Prefetching more means we will have to evict more. What to evict? [today’s focus]

slide-50
SLIDE 50

Replacement Policy

Want to maximize hit rate?
 Optimal strategy: evict pages to be accessed furthest in future Example Workload: 1,2,3,4,1,2,3,4,3,2,1

slide-51
SLIDE 51

Problem 4: optimal algorithm

Access Hit State (after) 1 2 3 4 1 2 3 4 3 2 1

assume cache size 3

slide-52
SLIDE 52

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no ??? 1 2 3 4 3 2 1

assume cache size 3

slide-53
SLIDE 53

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,4 1 2 3 4 3 2 1

assume cache size 3

slide-54
SLIDE 54

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,4 1 2 3 4 3 2 1

Worksheet assume cache size 3

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SLIDE 55

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,4 1 yes 1,2,4 2 yes 1,2,4 3 no 2,3,4 4 yes 2,3,4 3 yes 2,3,4 2 yes 2,3,4 1 no …

assume cache size 3

slide-56
SLIDE 56

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,4 1 yes 1,2,4 2 yes 1,2,4 3 no 2,3,4 4 yes 2,3,4 3 yes 2,3,4 2 yes 2,3,4 1 no …

assume cache size 3 Worksheet: hit rate?

slide-57
SLIDE 57

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,4 1 yes 1,2,4 2 yes 1,2,4 3 no 2,3,4 4 yes 2,3,4 3 yes 2,3,4 2 yes 2,3,4 1 no …

assume cache size 3

no fair! compulsory miss

slide-58
SLIDE 58

Problem 4: optimal algorithm

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,4 1 yes 1,2,4 2 yes 1,2,4 3 no 2,3,4 4 yes 2,3,4 3 yes 2,3,4 2 yes 2,3,4 1 no …

assume cache size 3

no fair! compulsory miss

Worksheet: hit rate modulo compulsory?

slide-59
SLIDE 59

FIFO

Items are evicted in the order they are inserted

  • Same example…
slide-60
SLIDE 60

Problem 5: FIFO

Access Hit State (after) 1 2 3 4 1 2 3 4 3 2 1

assume cache size 3

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SLIDE 61

Problem 5: FIFO

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no ??? 1 2 3 4 3 2 1

assume cache size 3

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SLIDE 62

Problem 5: FIFO

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 2,3,4 1 2 3 4 3 2 1

assume cache size 3 Worksheet

slide-63
SLIDE 63

Problem 5: FIFO

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 2,3,4 1 no 3,4,1 2 no 4,1,2 3 no 1,2,3 4 no 2,3,4 3 yes 2,3,4 2 yes 2,3,4 1 no 3,4,1

assume cache size 3

slide-64
SLIDE 64

Problem 6: more FIFO

Access Hit State (after) 1 2 3 4 1 2 5 1 2 3 4 5

Worksheet (a) cache size 3 (b) cache size 4

slide-65
SLIDE 65

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 2,3,4 1 no 3,4,1 2 no 4,1,2 5 no 1,2,5 1 yes 1,2,5 2 yes 1,2,5 3 no 2,5,3 4 no 5,3,4 5 yes 5,3,4

(a) size 3 (b) size 4

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,3,4 1 yes 1,2,3,4 2 yes 1,2,3,4 5 no 2,3,4,5 1 no 3,4,5,1 2 no 4,5,1,2 3 no 5,1,2,3 4 no 1,2,3,4 5 no 2,3,4,5

slide-66
SLIDE 66

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 2,3,4 1 no 3,4,1 2 no 4,1,2 5 no 1,2,5 1 yes 1,2,5 2 yes 1,2,5 3 no 2,5,3 4 no 5,3,4 5 yes 5,3,4

(a) size 3 (b) size 4

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,3,4 1 yes 1,2,3,4 2 yes 1,2,3,4 5 no 2,3,4,5 1 no 3,4,5,1 2 no 4,5,1,2 3 no 5,1,2,3 4 no 1,2,3,4 5 no 2,3,4,5

slide-67
SLIDE 67

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 2,3,4 1 no 3,4,1 2 no 4,1,2 5 no 1,2,5 1 yes 1,2,5 2 yes 1,2,5 3 no 2,5,3 4 no 5,3,4 5 yes 5,3,4

(a) size 3 (b) size 4

Access Hit State (after) 1 no 1 2 no 1,2 3 no 1,2,3 4 no 1,2,3,4 1 yes 1,2,3,4 2 yes 1,2,3,4 5 no 2,3,4,5 1 no 3,4,5,1 2 no 4,5,1,2 3 no 5,1,2,3 4 no 1,2,3,4 5 no 2,3,4,5

Belady’s Anomaly

slide-68
SLIDE 68

LRU, MRU

LRU: evict least-recently used


  • consider history
  • MRU: evict most-recently used
slide-69
SLIDE 69

LRU, MRU

Count hits for four combos:

  • Policy: LRU or MRU (both size 3)
  • Workloads:

1,2,3,4,3,4,3,4 AND 1,2,3,4,1,2,3,4

slide-70
SLIDE 70

LRU, MRU

Count hits for four combos:

  • Policy: LRU or MRU (both size 3)
  • Workloads:

1,2,3,4,3,4,3,4 AND 1,2,3,4,1,2,3,4

worksheet! (problem 7)

slide-71
SLIDE 71

Discuss

Can Belady’s anomaly happen with LRU?

slide-72
SLIDE 72

Discuss

Can Belady’s anomaly happen with LRU?

  • Stack property: smaller cache always subset of bigger
slide-73
SLIDE 73

Discuss

Can Belady’s anomaly happen with LRU?

  • Stack property: smaller cache always subset of bigger
  • Does optimal have stack property?
slide-74
SLIDE 74

LRU Hardware Support

What is needed?

slide-75
SLIDE 75

LRU Hardware Support

What is needed?

  • Timestamps. Why can’t OS alone track this?
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SLIDE 76

LRU Hardware Support

What is needed?

  • Timestamps. Why can’t OS alone track this?
  • Cheap approximation: reference (or use) bits.
  • set upon access, cleared by OS
  • useful for clock algorithm
slide-77
SLIDE 77

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=1 use=1 use=0 use=1

clock hand

slide-78
SLIDE 78

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=0 use=1 use=0 use=1

clock hand

slide-79
SLIDE 79

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=0 use=0 use=0 use=1

clock hand

slide-80
SLIDE 80

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=0 use=0 use=0 use=1

clock hand

evict page 2 because it has not been recently used

slide-81
SLIDE 81

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=0 use=0 use=0 use=1

clock hand

slide-82
SLIDE 82

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=1 use=0 use=0 use=1

clock hand

page 0 is accessed

slide-83
SLIDE 83

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=1 use=0 use=0 use=1

clock hand

slide-84
SLIDE 84

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=1 use=0 use=0 use=1

clock hand

slide-85
SLIDE 85

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=1 use=0 use=0 use=0

clock hand

slide-86
SLIDE 86

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=0 use=0 use=0 use=0

clock hand

slide-87
SLIDE 87

Clock: Look For a Page

1 2 3 …

Physical Mem:

use=0 use=0 use=0 use=0

clock hand

evict page 1 because it has not been recently used

slide-88
SLIDE 88

Other factors

Assume page is both in RAM and on disk

  • Do we have to write to disk for eviction?
slide-89
SLIDE 89

Other factors

Assume page is both in RAM and on disk

  • Do we have to write to disk for eviction?
  • not if page is clean
  • track with dirty bit
slide-90
SLIDE 90

Thrashing

A machine is thrashing when there is not enough RAM, and we constantly swap in/out pages

  • Solutions?
slide-91
SLIDE 91

Thrashing

A machine is thrashing when there is not enough RAM, and we constantly swap in/out pages

  • Solutions?
  • admission control (like scheduler project)
  • buy more memory
  • Linux out-of-memory killer!
slide-92
SLIDE 92

Summary

Virtual memory abstraction:

  • big address space
  • possible to fill address space, even with small RAM!
  • Many policy decisions:
  • what to prefetch
  • what to evict
  • how much to evict
slide-93
SLIDE 93

Announcements

One easy piece done!

  • Shell due Friday.
  • Lab office hours now.