In this module we would review a typical gate first, poly-Si gate CMOS process flow. 456
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The purpose of shallow trench isolation (STI) is to provide isolation between individual devices in a CMSO chip. Typical process details and the purpose of steps are given below: 1. RCA cleaning of the wafers 2. Pad oxide, ~ 15 nm, to relieve stress between Si and nitride, thermal oxidation 3. Nitride, ~ 150nm, as an etch stop for chemical mechanical polishing (CMP). Thermal CVD. 4. Active area lithography (193 nm litho), reactive ion etch to etch nitride, oxide and Silicon, Trench depth in Si ~ 400 nm. The trench sidewalls are slightly slanted. Resist strip. 5. RCA cleaning of the wafers. 6. Sidewall oxidation and corner rounding, high temperature thermal oxidation in in-situ generated steam (pyrogenic oxidation), corner round by viscous flow of the oxide at high temperature, ~ 20nm. 7. Deposition of trench fill oxide, ~ 550 nm, high density plasma oxide deposited by inductively coupled plasma CVD. Trench fill by deposition and etch. 8. Oxide CMP (chemical mechanical polish) stopping on nitride. Chemical mechanical polish process was discussed as part of the wafer manufacturing process. Scrubbing to remove contaminants from CMP slurry. 9. Oxide recess by wet etching – HF 10. Nitride removal by hot phosphoric acid, ~ 165 C. 459
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We would assume that a twin well technology is being used. So the n-channel devices would be made in a p-well and the p-channel devices would be made in a n-well. This particular module is simple. The p-well is masked during the n-well implant. Note that the STI liner/pad oxide is used as the implant screen oxide in this case. Various implants carried out in this step are: Well implants (deep implants) Anti punch through implants (medium depth) Threshold voltage adjust implant (shallow depth) The details would depend on the desired device characteristics. An oxidation/anneal is optionally done to activate the dopants and to remove implant damage if any. Many a time the implant activation is carried out in a slightly oxidizing ambient and it is seen that the sheet resistance obtained are better than in an inert ambient. 461
The implant screening oxide is removed. Usually the gate oxidation and poly-Si deposition are carried out in a multi chamber cluster tool. You had seen 3 examples when you visited the CEN. The poly-Si deposited is undoped. Typical thickness is in the range of 100 – 150 nm. Straight sidewalls with 90 degree slope is desirable for poly-Si gate. The poly- Si etch should be highly selective to SiO 2 which is used as the gate dielectric in our example. Re-oxidation is carried out to remove any damage that might have happened to the Si surface. This process is a thermal oxidation step at relatively low temperature like 750 C. 462
The purpose of the halo implant is to control short channel effects and hence to improve device scalability. The halo also improves the manufacturability of the process by reducing the sensitivity of threshold voltage to gate length around the nominal shortest gate length device in the technology. Extension implants form the shallow source and drain junctions. This implant has to be distinguished from the deep sour/drain implant that we would discuss in a subsequent slide. The shallow source/drain regions would control the short channel effects of the devices. In generic terms, shallower the extension junction, better is the short channel behavior. However a shallower junction region would also have higher sheet resistance. So a good compromise has to be reached. Typically the implant and anneal have to be optimized together to obtain good short channel effect control and low sheet resistance. Arsenic is used for the extension of the n-channel device. Obtaining shallow p- type implants is a challenge as Boron diffuses fast in Si. Some of the options are BF 2 implant, amorphization of the extension regions by Ge or Si implants prior to Boron implant, implantation of carbon to retard Boron diffusion etc. 463
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